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Noise Margin Based Library Optimization Considering Variability in Sub-threshold

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2012)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 7606))

Abstract

Operating at near-threshold voltage is an attractive solution for energy reduction in wireless sensor nodes, where throughput is often in the order of MBaud. The challenges at low supply voltages are timing or functional failures due to variability. A common mitigation technique is to apply cell pruning based on stack height or complexity. We present a new variability-aware methodology based on the static unity gain noise margin and its corresponding closed-form expression that enables cell selection and/or optimization for reliable low-voltage operation. Using a standard cell library in a 40nm low-power CMOS process as vehicle, the minimal supply voltage could be lowered by 70mV, or the library complexity increased without impacting reliability.

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Gemmeke, T., Ashouei, M., Noll, T.G. (2013). Noise Margin Based Library Optimization Considering Variability in Sub-threshold. In: Ayala, J.L., Shang, D., Yakovlev, A. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36157-9_8

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  • DOI: https://doi.org/10.1007/978-3-642-36157-9_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-36156-2

  • Online ISBN: 978-3-642-36157-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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