Abstract
Due to the increasing algorithmic complexity of today’s embedded systems, consideration of extra-functional properties becomes more important. Extra-functional properties like timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gate-level several techniques are available, but there is still a lack of methods and tools for power estimation and analyses at system and higher levels. In this paper we present an approach for non-invasive augmentation of functional SystemCTM TLM-2.0 components with power properties. The I/O behaviour of a TLM-2.0 component will be observed by a Protocol State Machine (PrSM) that generates trigger events to stimulate a Power State Machines (PSM). The PSM describes the component’s internal power states and transitions and transitions between them. Each component’s PSM is connected with a frequency and voltage dependent power model. We present first evaluation results of different IP components and compare our system-level power traces generation with state-of-the-art gate-level power simulations in terms of accuracy and simulation speed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Cai, L., Gajski, D.: Transaction level modeling: an overview. In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, pp. 19–24. ACM, New York (2003)
IEEE Computer Society: IEEE Standard SystemC Language Reference Manual. IEEE Std 1666–2011 (2011) ISBN 978-0-7381-6802-9
Walravens, C., Vanderperren, Y., Dehaene, W.: ActivaSC: A highly efficient and non-intrusive extension for activity-based analysis of SystemC models. In: 46th ACM/IEEE Design Automation Conference (DAC 2009), pp. 172–177 (July 2009)
Benini, L., Hodgson, R., Siegel, P.: System-level power estimation and optimization. In: International Symposium on Low Power Electronics and Design, ISLPED 1998, pp. 173–178. ACM, Monterey (1998)
Giammarini, M., Orcioni, S., Conti, M.: Powersim: Power Estimation with SystemC. In: Conti, M., et al. (eds.) Solutions on Embedded Systems. LNEE, vol. 81, pp. 285–300. Springer Science+Business Media, B.V. (2011)
Lebreton, H., Vivet, P.: Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. In: IEEE Annual Symposium on VLSI, ISVLSI 2008, pp. 463–466. IEEE Computer Society (April 2008)
Streubühr, M., Rosales, R., Hasholzner, R., Haubelt, C., Teich, J.: ESL Power and Performance Estimation for Heterogeneous MPSoCs Using SystemC. In: Forum on specification and Design Languages (FDL 2011), Oldenburg, Germany, pp. 202–209. IEEE Computer Society (September 2011)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lorenz, D., Hartmann, P.A., Grüttner, K., Nebel, W. (2013). Non-invasive Power Simulation at System-Level with SystemC. In: Ayala, J.L., Shang, D., Yakovlev, A. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36157-9_3
Download citation
DOI: https://doi.org/10.1007/978-3-642-36157-9_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36156-2
Online ISBN: 978-3-642-36157-9
eBook Packages: Computer ScienceComputer Science (R0)