Abstract
This work presents a simulated ultra-low-power 16-bit sub-threshold microprocessor designed in a 90nm CMOS technology. Transmission gate logic extended with transistor stacking is used for its high robustness to inter- and intra-die variations, while combining low power and small area. In a first implementation, the sub-threshold microprocessor has a throughput of 1MIPS at a 4MHz clock and a 150mV supply with an energy per instruction of 0.74pJ. Improved results are obtained using pipelining, which allows the microprocessor to achieve a maximum performance of 2MIPS, an energy consumption of 0.48pJ per instruction, an EDP of 0.23pJ×μs and a 0.9μW power consumption.
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Weckx, P., Reynders, N., de Moffarts, I., Dehaene, W. (2013). Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor. In: Ayala, J.L., Shang, D., Yakovlev, A. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36157-9_18
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DOI: https://doi.org/10.1007/978-3-642-36157-9_18
Publisher Name: Springer, Berlin, Heidelberg
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Online ISBN: 978-3-642-36157-9
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