Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor

  • Chuan Zhou
  • Yuzhuo Fu
  • Jiang Jiang
  • Xing Han
  • Kaikai Yang
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 337)


To efficiently maintain cache coherence in a many-core processor remains a big challenge today. Traditional protocols either offer low cache miss latency (like snoopy protocol) or not depending on bus-like interconnects (like directory protocol). Recently, Token Coherence has been proposed to capture the main characteristic of traditional protocols. However, since Token Coherence relies on broadcast-based transient request and inefficient persistent request, it is only suitable for small system. In order to make Token Coherence be scalable in many-core architectures, in this paper we introduce a dynamically reconfigurable mechanism to Token Coherence. Basing on sub-net, this mechanism can significantly reduce the average execution time and communication cost in 16-core processor. Therefore, this dynamically reconfigurable mechanism makes Token Coherence applicable in many-core architecture.


cache coherence token coherence dynamically reconfigurable sub-netting 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Chuan Zhou
    • 1
  • Yuzhuo Fu
    • 1
  • Jiang Jiang
    • 1
  • Xing Han
    • 1
  • Kaikai Yang
    • 1
  1. 1.School of MicroelectronicsShanghai Jiao Tong UniversityShanghaiChina

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