Advertisement

MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processor

  • Xiaobo Yan
  • Rangyu Deng
  • Caixia Sun
  • Qiang Dou
Part of the Communications in Computer and Information Science book series (CCIS, volume 337)

Abstract

With the widely application of multi-core multi-thread processor in various computing fields, simulation and verification of processors become increasingly important. In this paper, a multi-level hybrid verification platform called MGTE is designed and developed for a 16-core processer PX-16. MGTE supports software simulating and hardware emulating in module level, sub-system level or full-chip level, which is capable of verifying the processor during all the design periods from details to the whole. Also, MGTE supports the hybrid verification of behavior models, RTL codes and net lists, which is capable of improving the simulation performance. It’s proved that MGTE can effectively ease the functional verification and preliminary performance evaluation of PX-16 processor.

Keywords

Multi-core Multi-thread Processor Multi-level Hybrid Verification Verification platform 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Hu, J., et al.: A Study on CPU Chip-Oriented Verification Technology. Microelectronics 37(1), 16–23 (2007)Google Scholar
  2. 2.
    OpenSPARCTM T2 Core Microarchitecture Specification, Revision A. Sun Microsystems, Inc. (December 2007)Google Scholar
  3. 3.
    Nussbaum, D., Fedorova, A., Small, C.: An overview of the Sam CMT simulator kit. Sun Microsystems, Inc., Mountain View (2004)Google Scholar
  4. 4.
    Austin, T.M., Larson, E., Ernst, D.: Simplescalar: An infrastructure for computer system modeling. IEEE Computer 35(2), 59–67 (2002)CrossRefGoogle Scholar
  5. 5.
    OpenSPARCTM T2 Processor Design and Verification User’s Guide, Revision A, Sun Microsystems, Inc. (2008)Google Scholar
  6. 6.
    Synopsys VCSTM training, Synopsys, Inc. (2008)Google Scholar
  7. 7.
    Verilog Simulation User Guide, Product Version 9.2, Cadence, Inc. (July 2010)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Xiaobo Yan
    • 1
  • Rangyu Deng
    • 1
  • Caixia Sun
    • 1
  • Qiang Dou
    • 1
  1. 1.School of Computer ScienceNational University of Defense TechnologyChangshaChina

Personalised recommendations