Abstract
Coarse-Grained Reconfigurable Architectures (CGRAs) provide more opportunities for accelerating data-intensive applications, such as multi-media programs. However, the optimization of critical loops is still challenging issues, since there is lack of application mapping tool of CGRAs. To address this challenge, we first take program feature analysis on the kernel loops of applications. And then we propose a novel graph model called PIA-CDTG containing these features. We implement an efficient task mapping method with a genetic algorithm based on the graph model. Experimental results show that the mapping method with PIA-CDTG is more effective than other features-unaware methods, and make the execution attains high efficiency and availability.
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Yang, Z., Yan, M., Wang, D., Li, S. (2013). A Novel Graph Model for Loop Mapping on Coarse-Grained Reconfigurable Architectures. In: Xu, W., Xiao, L., Lu, P., Li, J., Zhang, C. (eds) Computer Engineering and Technology. NCCET 2012. Communications in Computer and Information Science, vol 337. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35898-2_25
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DOI: https://doi.org/10.1007/978-3-642-35898-2_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-35897-5
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