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A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method

  • Yuan Li
  • Jiang Jiang
  • Minxuan Zhang
  • Shaojun Wei
Part of the Communications in Computer and Information Science book series (CCIS, volume 337)

Abstract

In this paper, we proposed a hardware Gaussian random number generator based on the Box-Muller method. To reduce the resource complexity, an efficient word-length optimization model is proposed to find out the optimal word-lengths for signals. Experimental results show that our word-length optimized Fixed-Point generator runs as fast as 403.7 MHz on a Xilinx Virtex-6 FPGA device and is capable of generating 2 samples every clock cycle, which is 12.6 times faster compared to its corresponding dedicated software version. It uses up 442 Slices, 1517 FFs and 1517 LUTs, which is only about 1% of the device and saves almost 85% and 71% of area in comparison to the corresponding IEEE double & single Floating-Point generators, respectively. The statistical quality of the Gaussian samples produced by our design is verified by the common empirical test: the chi-square (X 2) test.

Keywords

Box-Muller Method Hardware Gaussian Random Number Generator FPGA Word-Length Optimization 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Yuan Li
    • 1
  • Jiang Jiang
    • 2
  • Minxuan Zhang
    • 1
  • Shaojun Wei
    • 3
  1. 1.School of ComputerNational University of Defense TechnologyChangshaP.R. China
  2. 2.Institute of MicroelectronicsShanghai Jiao Tong UniversityShanghaiP.R. China
  3. 3.Institute of MicroelectronicsTsinghua UniversityBeijingP.R. China

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