A High Performance DSP System with Fault Tolerant for Space Missions
Space missions are very demanding on system reliability. As the development of space-based remote sensor technologies, space missions are increasingly high required on system performance. Conventional techniques mainly focus on the system reliability, at the expense of system performance.
In this paper, a flexible, DPS-based, high-performance system is presented. The system could dynamically adapt the system’s level of redundancy according to varying radiation levels. A compare-point and fast recovery mechanism is proposed to improve system performance. Besides, some design ideas and implementation methods also be mentioned. In this paper, the system performances are evaluated and analyzed. With running of the correlation function benchmark in this system, it is shown that the system provides high performances under the premise of certified reliability.
Keywordscompare-point fast recovery high-performance space missions fault tolerance
Unable to display preview. Download preview PDF.
- 1.Jacobs, A., George, A.D., Cieslewski, G.: Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space. In: Field Programmable Logic and Applications (FPL), pp. 199–204 (August 2009)Google Scholar
- 2.Yousuf, S., Jacobs, A., Gordon-Ross, A.: Partially reconfigurable system-on-chips for adaptive fault tolerance. In: Field-Programmable Technology (FPT), pp. 1–8 (December 2011)Google Scholar
- 3.Ramos, J., Brenner, D.W., Galica, G.E., Walter, C.J.: Environmentally Adaptive Fault Tolerant Computing (EAFTC). In: Aerospace Conference, pp. 1–10 (March 2005)Google Scholar
- 4.Samson, J., John, R., Ramos, J., George, A.D., Patel, M., Some, R.: Technology Validation: NMP ST8 Dependable Multiprocessor Project II. In: Aerospace Conference, pp. 1–18 (March 2007)Google Scholar
- 5.Yang, J., Xing, K.F., Zhang, C.S.: Design of Reconfigurable Space Information Processing Platform. In: 7th National Information Gathering and Processing Meeting, pp. 723–726 (June 2009)Google Scholar
- 6.Abate, F., Sterpone, L., Lisboa, C.A., Carro, L., Violante, M.: New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA Embedded Processors. In: Nuclear Science, pp. 1992–2000 (August 2009)Google Scholar
- 7.Texas Instruments: TMS320C64x Image/Video Processing Library Programmer’s Reference. SPRUEB9 (March 2006)Google Scholar
- 9.Matthew, J.W.: Using Commercial Off the Shelf (COTS) Digital Signal Processors (DSP) for Reliable Space Based Digital Signal Processing. Naval Postgraduate School (2001)Google Scholar