A Configurable Architecture for 1-D Discrete Wavelet Transform

  • Qing Sun
  • Jiang Jiang
  • Yuzhuo Fu
Part of the Communications in Computer and Information Science book series (CCIS, volume 337)


This work presents a novel configurable architecture for 1-dimensional discrete wavelet transform (DWT) which can be configured into different types of filters with different lengths. The architecture adopts polyphase filter structure and MAC loop based filter (MLBF) to achieve high computing performance and strong generality of the system. Loop unrolling approach is used to eliminate the data hazards caused by pipelining. The hardware usage of the configurable architecture is fixed for any kind of wavelet functions.


1-D DWT Configurable circuit VLSI FPGA 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Kotteri, K.A., et al.: A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting. IEEE Circuits and Systems II: Express BriefsGoogle Scholar
  2. 2.
    Mallat, S.G.: A theory for multiresolution signal decomposition: the wavelet representation. IEEE Transactions on Pattern Analysis and Machine Intelligence 11, 674–693 (1989)zbMATHCrossRefGoogle Scholar
  3. 3.
    Daubechies, I., Sweldens, W.: Factoring wavelet transforms into lifting steps. Journal of Fourier Analysis and Applications 4, 247–269 (1998)MathSciNetzbMATHCrossRefGoogle Scholar
  4. 4.
    Vishwanath, M.: The recursive pyramid algorithm for the discrete wavelet transform. IEEE Transactions on Signal Processing 42, 673–676 (1994)CrossRefGoogle Scholar
  5. 5.
    Chao-Tsung, H., et al.: Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Transactions on Signal Processing 52, 1080–1089 (2004)MathSciNetCrossRefGoogle Scholar
  6. 6.
    Mallat, S.G.: Multifrequency channel decompositions of images and wavelet models. IEEE Transactions on Acoustics, Speech and Signal Processing 37, 2091–2110 (1989)CrossRefGoogle Scholar
  7. 7.
    Chakrabarti, C., Vishwanath, M.: Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to mapping on SIMD array computers. IEEE Trans. Signal Process. 43(3), 759–771 (1995)CrossRefGoogle Scholar
  8. 8.
    Grzesczak, A., Mandal, M.K., Panchanathan, S.: VLSI implementation of discrete wavelet transform. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 4(4), 421–433 (1996)CrossRefGoogle Scholar
  9. 9.
    Marino, F., Guevorkian, D., Astola, J.: Highly efficient high-speed/low-power architectures for 1-D discrete wavelet transform. IEEE Trans. Circuits Syst. II, Exp. Briefs 47(12), 1492–1502 (2000)CrossRefGoogle Scholar
  10. 10.
    Park, T.: Efficient VLSI architecture for one-dimensional discrete wavelet transform using a scalable data recorder unit. In: Proc. ITC-CSCC, Phuket, Thailand, pp. 353–356 (July 2002)Google Scholar
  11. 11.
    Chengjun, Z., et al.: A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform. IEEE Transactions on Circuits and Systems I: Regular Papers 57, 2729–2740 (2010)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Qing Sun
    • 1
  • Jiang Jiang
    • 1
  • Yuzhuo Fu
    • 1
  1. 1.School of MicroelectronicsSJTUShanghaiP.R. China

Personalised recommendations