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A Hardware Implementation of Nussinov RNA Folding Algorithm

  • Qilong Su
  • Jiang Jiang
  • Yuzhuo Fu
Part of the Communications in Computer and Information Science book series (CCIS, volume 337)

Abstract

The RNA secondary structure prediction, or RNA folding, is a compute-intensive task that is used in many bioinformatics applications. Developing the parallelism of this kind of algorithms is one of the most relevant areas in computational biology. In this paper, we propose a parallel way to implement the Nussinov algorithm on hardware. We implement our work on Xilinx FPGA, the total clock cycles to accomplish the algorithm is about half of using software in serial way, and we also partly resolve the limitation of fixed length requirement of existing hardware implementation with an efficient resource usage.

Keywords

Nussinov algorithm vector operand hardware implementation 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Qilong Su
    • 1
  • Jiang Jiang
    • 1
  • Yuzhuo Fu
    • 1
  1. 1.School of MicroelectronicsShanghai Jiao Tong UniversityShanghaiChina

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