A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU
It is a long-time discussed problem that the balancing of global multi-mode clock tree is. And there are many potential problems caused by the unbalanced clock tree, such as timing violations, density and power comsuption. In this article, an innovative balance method is opened by adopting the redundance clock mux. The basic idea of it is to maximize the reuse of the clock tree for other modes and keep the sub-clock tree within the sub-blocks unchanged. A demo chip on 40nm process has this balance skill verified, and makes the density, leakage and power comsuption deeply decreased.
KeywordsUltra-large Scale CPU clock tree balancing multi-mode
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- 1.Xiao, L.F., Xiao, Z.G., Qian, Z.C., Jiang, Y., Huang, T., Tian, H.T., et al.: Local clock skew minimization using blockage-aware mixed tree-mesh clock network. In: 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 458–462 (2010)Google Scholar
- 2.Fu, Q., Luk, W.S., Zhao, W.Q., Chen, S.J., Zeng, X.: Local refinement method for optimizing clock tree topology. In: 7th International Conference on ASIC, ASICON 2007, pp. 1110–1113 (2007)Google Scholar
- 4.Tsai, C.C., Lin, T.H., Tsai, S.H., Chen, H.M.: Clock planning for multi-voltage and multi-mode designs. In: 2011 12th International Symposium on Quality Electronic Design (ISQED), pp. 1–5 (2011)Google Scholar
- 5.Chen, Y.P., Wong, D.F.: An algorithm for zero-skew clock tree routing with buffer insertion. In: Proceedings of the European Design and Test Conference, ED&TC 1996, pp. 230–236 (1996)Google Scholar
- 6.Sulaiman, M.S.: A balanced clock network design algorithm for clock delay, skew, and power optimization with slew rate constraint. In: Proceedings of the IEEE International Conference on Semiconductor Electronics, ICSE 2002, pp. 62–66 (2002)Google Scholar