Low-Cost Dynamic Voltage and Frequency Management Based upon Robust Control Techniques under Thermal Constraints

  • Sylvain Durand
  • Suzanne Lesecq
  • Edith Beigné
  • Christian Fabre
  • Lionel Vincent
  • Diego Puschini
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7542)


Mobile computing platforms need ever increasing perfor–mance, which implies an increase in the clock frequency applied to the processing elements (PE). As a consequence, the distribution of a single global clock over the whole circuit is tremendously difficult. Globally Asynchronous Locally Synchronous (GALS) designs alleviate the problem of clock distribution by having multiple clocks, each one being distributed on a small area of the chip. Energy consumption is the main limiting factor for mobile platforms as they are powered by batteries. Dynamic Voltage and Frequency Scaling (DVFS) in each Voltage and Frequency Island (VFI) has proven to be highly effective to reduce the power consumption of the chip while meeting the performance requirements. Environmental parameters (i.e. temperature and supply voltage) changes also strongly affect the chip performance and its power consumption. Some sensors can be buried in order to estimate via data fusion techniques the supply voltage and the temperature variations. For instance the knowledge of the gap between the temperature and its maximum value can be used to adapt the power management technique. The present paper deals with the design of a voltage and frequency management approach (DVFS) that explicitly takes into account the thermal constraints of the platform.


Model Predictive Control Duty Ratio Dynamic Voltage Dynamic Voltage Scaling Thermal Constraint 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Liu, Y., Yang, H., Dick, R.P., Wang, H., Shang, L.: Thermal vs energy optimization for dvfs-enabled processors in embedded systems. In: 8th International Symposium on Quality Electronic Design, ISQED 2007 (2007)Google Scholar
  2. 2.
    Hanumaiah, V., Vrudhula, S.: Temperature-aware dvfs for hard real-time applications on multi-core processors. IEEE Transactions on Computers (2011)Google Scholar
  3. 3.
    Durand, S.: Reduction of the Energy Consumption in Embedded Electronic Devices with Low Control Computational Cost. PhD thesis, University of Grenoble, France (2011)Google Scholar
  4. 4.
    Zhuravlev, S., Saez, J.C., Blagodurov, S., Fedorova, A., Prieto, V.: Survey of energy-cognizant scheduling techniques. IEEE Transactions on Parallel and Distributed Systems (2012)Google Scholar
  5. 5.
    Tschanz, J., Kao, J., Narendra, S., Nair, R., Antoniadis, D., Chandrakasan, A., De, V.: Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. In: 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, vol. 1, pp. 422–478 (2002)Google Scholar
  6. 6.
    Firouzi, F., Yazdanbakhsh, A., Dorosti, H., Fakhraie, S.M.: Dynamic soft error hardening via joint body biasing and dynamic voltage scaling. In: 2011 14th Euromicro Conference on Digital System Design, DSD, August 31-September 2, pp. 385–392 (2011)Google Scholar
  7. 7.
    Mehta, N., Amrutur, B.: Dynamic supply and threshold voltage scaling for cmos digital circuits using in-situ power monitor. IEEE Transactions on Very Large Scale Integration (VLSI) Systems PP(99), 1–10 (2011)Google Scholar
  8. 8.
    Horowitz, M., Indermaur, T., González, R.: Low-power digital design. In: IEEE Symposium on Low Power Electronics, Digest of Technical Papers, pp. 8–11 (October 1994)Google Scholar
  9. 9.
    Choudhary, P., Marculescu, D.: Hardware based frequency/voltage control of voltage frequency island systems. In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, pp. 34–39 (October 2006)Google Scholar
  10. 10.
    Choi, K., Soma, R., Pedram, M.: Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(1), 18–28 (2005)CrossRefGoogle Scholar
  11. 11.
    Sabry, M., Coskun, A., Atienza, D., Simunic Rosing, T., Brunschwiler, T.: Energy-efficient multi-objective thermal control for liquid-cooled 3D stacked architectures. IEEE Transactions on Computer Aided Design (2011)Google Scholar
  12. 12.
    Wang, X., Ma, K., Wang, Y.: Adaptive power control with online model estimation for chip multiprocessors. IEEE Trans. on Parallel and Distributed Systems 29(10), 1681–1696 (2011)CrossRefGoogle Scholar
  13. 13.
    Chen, P., Chen, C.-C., Tsai, C.-C., Lu, W.-F.: A time-to-digital-converter-based cmos smart temperature sensor. IEEE Journal of Solid-State Circuits 40, 1642–1648 (2005)CrossRefGoogle Scholar
  14. 14.
    Aoki, H., Ikeda, M., Asada, K.: On-chip voltage noise monitor for measuring voltage bounce in power supply lines using a digital tester. In: International Conference on Microelectronic Test Structures, ICMTS (2000)Google Scholar
  15. 15.
    Datta, B., Burleson, W.: Low-power and robust on-chip thermal sensing using differential ring oscillators. In: 50th Midwest Symposium on Circuits and Systems, MWSCAS (2007)Google Scholar
  16. 16.
    Quenot, G., Paris, N., Zavidovique, B.: A temperature and voltage measurement cell for vlsi circuits. In: Euro ASIC 1991 (1991)Google Scholar
  17. 17.
    Vincent, L., Beigne, E., Alacoque, L., Lesecq, S., Bour, C., Maurine, P.: A fully integrated 32 nm multiprobe for dynamic pvt measurements within complex digital soc. In: VARI 2011, Grenoble, France (2011)Google Scholar
  18. 18.
    Vincent, L., Maurine, P., Lesecq, S., Beigné, E.: Embedding statistical tests for on-chip dynamic voltage and temperature monitoring. In: 49th ACM/EDAC/IEEE Design Automation Conference, DAC (2012)Google Scholar
  19. 19.
    Chandrakasan, A.P., Brodersen, R.W.: Minimizing power consumption in digital CMOS circuits. Proceedings of the IEEE 83(4), 498–523 (1995)CrossRefGoogle Scholar
  20. 20.
    Varma, A., Ganesh, B., Sen, M., Choudhury, S.R., Srinivasan, L., Bruce, J.: A control-theoretic approach to dynamic voltage scheduling. In: Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (2003)Google Scholar
  21. 21.
    Ishihara, T., Yasuura, H.: Voltage scheduling problem for dynamically variable voltage processors. In: Proceedings of the International Sympsonium on Low Power Electronics and Design (1998)Google Scholar
  22. 22.
    Miermont, S., Vivet, P., Renaudin, M.: A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. In: Azémard, N., Svensson, L. (eds.) PATMOS 2007. LNCS, vol. 4644, pp. 556–565. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  23. 23.
    Durand, S., Marchand, N.: Fully discrete control scheme of the energy-performance tradeoff in embedded electronic devices. In: Proceedings of the 18th World Congress of IFAC (2011)Google Scholar
  24. 24.
    Alamir, M.: Stabilization of Nonlinear Systems Using Receding-Horizon Control Schemes: A Parametrized Approach for Fast Systems. LNCIS, vol. 339. Springer, Heidelberg (2006)zbMATHGoogle Scholar
  25. 25.
    Kuzmicz, W., Piwowarska, E., Pfitzner, A., Kasprowicz, D.: Static power consumption in nano-cmos circuits: Physics and modelling. In: Proceeding of the 14th International Conference on Mixed Design of Integrated Circuits and Systems (2007)Google Scholar
  26. 26.
    Yang, C.-Y., Chen, J.-J., Lothar, T., Kuo, T.-W.: Energy-efficient real-time task scheduling with temperature-dependent leakage. In: Conference & Exhibition on Design, Automation and Test in Europe (2010)Google Scholar
  27. 27.
    Yuan, L., Leventhal, S., Qu, G.: Temperature-aware leakage minimization technique for real-time systems. In: IEEE/ACM International Conference on Computer-Aided Design (2006)Google Scholar
  28. 28.
    Chaturvedi, V., Huang, H., Quan, G.: Leakage aware scheduling on maximum temperature minimization for periodic hard real-time systems. In: 10th IEEE International Conference on Computer and Information Technology (2010)Google Scholar
  29. 29.
    Huang, H., Quan, G.: Leakage aware energy minimization for real-time systems under the maximum temperature constraint. In: Conference & Exhibition on Design, Automation and Test in Europe (2011)Google Scholar
  30. 30.
    Chaturvedi, V., Quan, G.: Leakage conscious DVS scheduling for peak temperature minimization. In: 16th Asia and South Pacific Design Automation Conference (2011)Google Scholar
  31. 31.
    Huang, H., Quan, G., Fan, J., Qiu, M.: Throughput maximizaion for periodic real-time systems under the maximal temperature constraint. In: 48th ACM/EDAC/IEEE Design Automation Conference (2011)Google Scholar
  32. 32.
    Quan, G., Zhang, Y.: Leakage aware feasibility analisys for temperature-constrained hard real-time periodic tasks. In: 21st Euromicro Conference on Real-Time Systems (2009)Google Scholar
  33. 33.
    Zhang, S., Chatha, K.S.: Approximation algorithm for the temperature-aware scheduling problem. In: IEEE/ACM International Conference on Computer-Aided Design (2007)Google Scholar
  34. 34.
    Erickson, R.W., Maksimović, D.: Fundamentals of Power Electronics, 2nd edn. Springer Science (2001)Google Scholar
  35. 35.
    Sridhar, A., Vincenzi, A., Ruggiero, M., Brunschwiler, T., Atienza, D.: 3D-ICE: Fast compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling. In: International Conference on Computer-Aided Design (2010)Google Scholar
  36. 36.
    Sridhar, A., Vincenzi, A., Ruggiero, M., Brunschwiler, T., Atienza, D.: Compact transient thermal model for 3D ICs with liquid cooling via enhanced heat transfer cavity geometries. In: 16th International Workshop on Thermal Investigations of ICs and Systems (2010)Google Scholar
  37. 37.
    Beigne, E., Vivet, P.: An innovative local adaptive voltage scaling architecture for on-chip variability compensation. In: IEEE Int. Conf. New Circuits and Systems, NEWCAS, pp. 510–513 (June 2011)Google Scholar
  38. 38.
    Albea, C., Puschini, D., Vivet, P., Miro Panades, I., Beigné, E., Lesecq, S.: Architecture and robust control of a digital frequency-locked loop for fine-grain dynamic voltage and frequency scaling in globally asynchronous locally synchronous structures. J. Low Power Electronics 7(3), 328–340 (2011)CrossRefGoogle Scholar
  39. 39.
    STMicroelectronics and CEA. Platform 2012 – A Manycore Programmable Accelerator for Ultra-Efficient Embedded Computing in Nanometer Technology (November 2010) (Whitepaper)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Sylvain Durand
    • 1
  • Suzanne Lesecq
    • 2
  • Edith Beigné
    • 2
  • Christian Fabre
    • 2
  • Lionel Vincent
    • 2
  • Diego Puschini
    • 2
  1. 1.NECS Team, INRIA/GIPSA-lab joint teamInovalléeSaint Ismier CedexFrance
  2. 2.LETI MINATEC CampusCEAGrenoble Cedex 9France

Personalised recommendations