Advertisement

Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields

  • Saptarsi Das
  • Ranjani Narayan
  • Soumitra Kumar Nandy
Part of the Communications in Computer and Information Science book series (CCIS, volume 314)

Abstract

In this paper we present a hardware-software hybrid technique for modular multiplication over large binary fields. The technique involves application of Karatsuba-Ofman algorithm for polynomial multiplication and a novel technique for reduction. The proposed reduction technique is based on the popular repeated multiplication technique and Barrett reduction. We propose a new design of a parallel polynomial multiplier that serves as a hardware accelerator for large field multiplications. We show that the proposed reduction technique, accelerated using the modified polynomial multiplier, achieves significantly higher performance compared to a purely software technique and other hybrid techniques. We also show that the hybrid accelerated approach to modular field multiplication is significantly faster than the Montgomery algorithm based integrated multiplication approach.

Keywords

Elliptic curve cryptography Binary fields Reduction Polynomial multiplication 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Koblitz, N.: Elliptic Curve Cryptosystems. Mathematics of Computation 48, 203–209 (1987)MathSciNetzbMATHCrossRefGoogle Scholar
  2. 2.
    Miller, V.S.: Use of Elliptic Curves in Cryptography. In: Williams, H.C. (ed.) CRYPTO 1985. LNCS, vol. 218, pp. 417–426. Springer, Heidelberg (1986)Google Scholar
  3. 3.
    Batina, L., Bruin-Muurling, G., Örs, S.: Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems. In: Okamoto, T. (ed.) CT-RSA 2004. LNCS, vol. 2964, pp. 250–263. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  4. 4.
    Saqib, N.A., Rodriguez-Henriquez, F., Diaz-Pirez, A.: A Parallel Architecture for Fast Computation of Elliptic Curve Scalar Multiplication over GF(2m). In: International on Parallel and Distributed Processing Symposium, vol. 4, p. 144a (2004)Google Scholar
  5. 5.
    Hinkelmann, H., Zipf, P., Li, J., Liu, G., Glesner, M.: On the Design of Reconfigurable Multipliers for Integer and Galois Field Multiplication. Microprocessors and Microsystems - Embedded Hardware Design 33, 2–12 (2009)CrossRefGoogle Scholar
  6. 6.
    Wu, H.: Bit-parallel Finite Field Multiplier and Squarer using Polynomial Basis. IEEE Transactions on Computers 51, 750–758 (2002)CrossRefGoogle Scholar
  7. 7.
    Ahlquist, G., Nelson, B., Rice, M.: Optimal Finite Field Multipliers for FPGAs. In: Lysaght, P., Irvine, J., Hartenstein, R.W. (eds.) FPL 1999. LNCS, vol. 1673, pp. 51–61. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  8. 8.
    Koç, Ç.K., Acar, T.: Montgomery Multiplication in GF(2k). Designs, Codes and Cryptography 14, 57–69 (1998)zbMATHCrossRefGoogle Scholar
  9. 9.
    Montgomery, P.: Modular Multiplication Without Trial Division. Mathematics of Computation 44, 519–521 (1985)MathSciNetzbMATHCrossRefGoogle Scholar
  10. 10.
    Karatsuba, A., Ofman, Y.: Multiplication of Multidigit Numbers on Automata. Soviet Physics—Doklady 7, 595–596 (1963)Google Scholar
  11. 11.
    Weimerskirch, A., Paar, C.: Generalizations of the Karatsuba Algorithm for Efficient Implementations. IACR Cryptology ePrint Archive 2006, 224 (2006)Google Scholar
  12. 12.
    Eberle, H., Gura, N., Shantz, S.C., Gupta, V.: A Cryptographic Processor for Arbitrary Elliptic Curves over GF(2m). Technical report, Mountain View, CA, USA (2003)Google Scholar
  13. 13.
    Satoh, A., Takano, K.: A Scalable Dual-Field Elliptic Curve Cryptographic Processor. IEEE Transactions on Computers 52, 449–460 (2003)CrossRefGoogle Scholar
  14. 14.
    Barrett, P.: Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor. In: Odlyzko, A.M. (ed.) CRYPTO 1986. LNCS, vol. 263, pp. 311–323. Springer, Heidelberg (1987)Google Scholar
  15. 15.
    Knežević, M., Sakiyama, K., Fan, J., Verbauwhede, I.: Modular Reduction in GF(2n) without Pre-computational Phase. In: von zur Gathen, J., Imaña, J.L., Koç, Ç.K. (eds.) WAIFI 2008. LNCS, vol. 5130, pp. 77–87. Springer, Heidelberg (2008)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Saptarsi Das
    • 1
  • Ranjani Narayan
    • 2
  • Soumitra Kumar Nandy
    • 1
  1. 1.Indian Institute of ScienceBangaloreIndia
  2. 2.Morphing Machines Pvt. LtdBangaloreIndia

Personalised recommendations