Abstract
Putting runtime verification into everyday industrial practice, shows the demand for formalisms that are easily understandable and usable, also for non-experts. To gain deeper insight into a system’s behaviour, methods must be sufficiently expressive and support the evaluation of quantitative properties. We present a graphical specification language for quantitative trace analysis based on timing diagrams to meet these requirements. The proposed formalism allows the verification of functional requirements against traces in combination with the determination of quantitative parameters that characterize the system and render original requirements more precisely. We successfully included the timing diagram specification formalism and the corresponding evaluation methods into commercial trace analysis and test tools which are used to examine measurement data from the industrial automation and automotive domains.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Finkbeiner, B., Sankaranarayanan, S., Sipma, H.B.: Collecting statistics over runtime executions. In: Proc. of Runtime Verification (RV 2002), pp. 36–55. Elsevier (2002)
Fisler, K.: Timing diagrams: Formalization and algorithmic verification. Journal of Logic, Language and Information 8, 323–361 (1999), doi:10.1023/A:1008345113376
Damm, W., Josko, B., Schlör, R.: Specification and validation methods, pp. 331–409. Oxford University Press, Inc., New York (1995)
Grass, W., Grobe, C., Lenk, S., Tiedemann, W.D., Kloos, C., Marin, A., Robles, T.: Transformation of timing diagram specifications into VHDL code. In: Design Automation Conference, Proc. ASP-DAC 1995/CHDL 1995/VLSI 1995 (1995)
Schlör, R.: Symbolic timing diagrams: a visual formalism for model verification. PhD thesis, Universität Oldenburg (2002)
Feyerabend, K.: Real time symbolic timing diagram. Technical report, Carl von Ossietzky Universität Oldenburg (1996)
Lenk, S.: Extended timing diagrams as a specification language. In: EURO-DAC 1994: Proceedings of the Conference on European Design Automation, pp. 28–33. IEEE Computer Society Press, Los Alamitos (1994)
Deutschmann, R., Fruth, M., Zabelt, M.: Neue Absicherungsstrategien für Steuergerätesoftware. In: Moderne Elektronik im Kfz V, Haus der Technik (2010)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Richter, A., Kabitzsch, K. (2013). Quantitative Trace Analysis Using Extended Timing Diagrams. In: Qadeer, S., Tasiran, S. (eds) Runtime Verification. RV 2012. Lecture Notes in Computer Science, vol 7687. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35632-2_15
Download citation
DOI: https://doi.org/10.1007/978-3-642-35632-2_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-35631-5
Online ISBN: 978-3-642-35632-2
eBook Packages: Computer ScienceComputer Science (R0)