Design Challenges in Power Handling Techniques in Nano Scale Cmos Devices

Abstract

VLSI design currently enables us to build million transistor chips. In the current and coming decades VLSI design will become highly complex. Minimization of power consumption is essential for high performance VLSI systems. In digital CMOS circuits there are three sources of power dissipation, the first is due to signal transition, the second source of power dissipation comes from short circuit current which flows directly from supply to ground terminal and the last is due to leakage currents. As technology scales down the short circuit power will be comparable to dynamic power dissipation. Furthermore, the leakage power shall also become highly significant. High leakage current in nano-scale regime is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modelling of different leakage components is very important for estimation and reduction of leakage power especially for low-power applications. 40% or even higher percentage of the total power consumption is due to the leakage in transistors [2]. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This paper focuses on different techniques such as run time and design time techniques are introduced to accomplish power. Handling in nano-scale CMOS devices and provides a detailed overview of these. SPICE results are given for two nano-regime technology nodes.