Abstract
In this paper, we have implemented a modified version of the Bypass Zero Feed A Directly (MODBZ-FAD) multiplier architecture based on shift- and add- method. This architecture has considerably low power than the other multiplier architectures. In this architecture we have reduced the power consumption and propagation delay of the circuit. This has been done by removing Bypass register,dflipflop & multiplexers. The synthesis results shows that the switching activity had been lowered up to 78% and power consumption up to 22% when compared up to BZ-FAD architecture.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Mottaghi-Dastjerdi, M., Afzali-Kusha, A., Pedram, M.: BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture. IEEE Transactions on Very Large Scale Integration (vlsi) Systems 17(2) (February 2009)
Yeap, G.: Motorola: Practical Low Power Digital VLSI Design. Kluwer Academic Publishers
Kayyalha, M., Namaki-Shoushtari, M., Dorosti, H.: BZ-FAD A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture
Marimuthu, C.N., Thangaraj, P., Ramesan, A.: Low Power Shift And Add Multiplier Design. International Journal of Computer Science and Information Technology 2(3) (June 2010)
Chen, O.T., Wang, S., Wu, Y.-W.: Minimization of switching activities of partial products for designing low-power multipliers. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11
Chandrakasan, A., Brodersen, R.: Lowpower CMOS digital design. IEEE J. Solid-State Circuits 27(4)
Marimuthu, C.N., Thangaraj, P.: Low Power High Performance Multiplier. In: ICGST-PDCS, vol. 8(1) (December 2008)
Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low-Power CMOS Digital Design. Journal of Solid State Circuits 27(4) (April 1992)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
About this paper
Cite this paper
G.R., D., Iyer, A., G.N., N. (2012). Modified Low-Power Multiplier Architecture. In: Das, V.V., Stephen, J. (eds) Advances in Communication, Network, and Computing. CNC 2012. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 108. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35615-5_25
Download citation
DOI: https://doi.org/10.1007/978-3-642-35615-5_25
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-35614-8
Online ISBN: 978-3-642-35615-5
eBook Packages: Computer ScienceComputer Science (R0)