Abstract
Dynamically reconfigurable FPGAs are being deployed for real time systems that not only adapt to run-time changes in the system load but also reconfigure their resources to minimize the adverse impact of faults. In this paper, we propose a systematic methodology for conducting a Design Space Exploration (DSE) of high availability mission-critical real time systems. Armed with abundant reconfigurable resources on the FPGA estate, the central challenge in this system design problem is to endow each task with the right degree of fault tolerance so as to sustain the most important services throughout the mission’s life.
Our scheme employs a two-stage strategy to tackle faults online: A suite of passive online Fault Tolerant (FT) techniques provide immediate mitigation when faults strike in order to sustain the required functionality. Next, a pre-planned fault diagnosis and repair procedure analyzes the faulty modules offline to localize them and, if required utilizes spare resources to recover from hard faults. The repaired modules are re-engaged to restore the original FT configurations. We employ a Genetic Algorithm(GA) to evolve a population of chromosomes representing a set of FT architectures for the given application. Experiments conducted on large representative task graphs reveal that the DSE system is able to steer the population towards high availability architectural solutions with potential tradeoff between area usage and availability.
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Chakraverty, S., Agarwal, A., Agarwal, A., Kumar, A., Sikri, A. (2012). Design Space Exploration for High Availability drFPGA Based Embedded Systems. In: Hassanien, A.E., Salem, AB.M., Ramadan, R., Kim, Th. (eds) Advanced Machine Learning Technologies and Applications. AMLTA 2012. Communications in Computer and Information Science, vol 322. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35326-0_24
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DOI: https://doi.org/10.1007/978-3-642-35326-0_24
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