Advertisement

A Delta-Sigma Converter for WLAN Using a TEQ

  • Richard Gaggl
Chapter
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 39)

Abstract

Modern CMOS technologies employ the high-speed performances of nanoscale transistors. The possible supply voltage results in typically one Volts for a device consisting of a gate-oxide thickness of about 1.2 nm. One of the main challenges is the implementation of the multi-bit quantizer with an array of comparators resulting in a flash-converter. The performance of these converters is bounded by the tolerable limit for the power consumption of the flash-converter embedded in multi-bit architectures. This flash-converter is quite problematic to realize in low-voltage technologies, where the dynamic range of the comparators is limited and comparator offset degrades the linearity of the quantizer. Furthermore, a multi-bit D/A-converter is required in the feedback path whereas its impairments limit the overall performance.

Keywords

Noise Transfer Function Signal Transfer Function Signal Swing Decimation Filter Excess Loop Delay 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Bibliography

  1. 1.
    A.A. Lazar, L.T. Toth, Time encoding and perfect recovery of bandlimited signals, in Proceedings of ICASSP, International Conference on Acoustics, Speech and Signal Processing (2003), pp. 709–712 Google Scholar
  2. 5.
    B. Razavi, RF Microelectronics (Prentice Hall, New Jersey, 1998) Google Scholar
  3. 7.
    E. Prefasi, S. Paton, L. Hernandez, A 7 mW 20 MHz BW time-encoding oversampling converter implemented in a 0.08 mm2 65 nm CMOS circuit. IEEE J. Solid-State Circuits 46(7), 1562–1574 (2011) CrossRefGoogle Scholar
  4. 8.
    E. Prefasi, S. Paton, L. Hernandez, R. Gaggl, A. Wiesbauer, J. Hauptmann, A 0.08 mm2, 7 mW time-encoding oversampling converter with 10 bits and 20 MHz BW in 65 nm CMOS, in Proceedings of the 36th ESSCIRC (2010), pp. 430–433 CrossRefGoogle Scholar
  5. 9.
    E. Roza, Analog to digital conversion via duty-cycle modulation. IEEE Trans. Circuits Syst. II 44(11), 907–914 (1997) CrossRefGoogle Scholar
  6. 10.
    E. Roza, Poly-phase sigma-delta modulation. IEEE Trans. Circuits Syst. II 44(11), 915–923 (1997) CrossRefGoogle Scholar
  7. 12.
    F. Colodro, A. Torralba, M. Laguna, Continuous-time sigma-delta modulator with an embedded pulsewidth modulation. IEEE Trans. Circuits Syst. I 55(3), 775–785 (2008) MathSciNetCrossRefGoogle Scholar
  8. 19.
    J. Daniels, Asynchronous delta-sigma A/D-converters: digital demodulation using a time-to- digital converter. Technical report, Katholieke Universiteit Leuven, ESAT-MICAS, 2005; internal report of colaboration between Infineon and KU Leuven, ESAT-MICAS Google Scholar
  9. 23.
    J.R. Higgins, R.L. Stens, Sampling Theory in Fourier and Signal Analysis (Oxford University Press, Oxford, 1996) zbMATHGoogle Scholar
  10. 24.
    J.S. Cherry, W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion (Kluwer Academic, Dordrecht, 2000) Google Scholar
  11. 31.
    L. Hernandez, E. Prefasi, Analog to digital conversion using noise shaping and time encoding. IEEE Trans. Circuits Syst. I 55(7), 2026–2037 (2008) MathSciNetCrossRefGoogle Scholar
  12. 35.
    M. Ortmanns, F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion. Springer Series in Advanced Microelectronics (Springer, Berlin, 2006) Google Scholar
  13. 45.
    Ph. Allen, D. Holberg, CMOS Analog Circuit Design (Oxford University Press, Oxford, 2002). ISBN 0-19-511644-5 Google Scholar
  14. 49.
    R. Joerg, Wireless LANs (Heise Zeitschriften, Hannover, 2006) Google Scholar
  15. 50.
    R. Schoofs, Design of High-Speed Continuous-Time Delta-Sigma A/D Converters for Broadband Communication (Katholieke Universiteit Leuven, Belgium, 2007). ISBN 978-90-5682-845-5 Google Scholar
  16. 53.
    R. Schreier, Delta-sigma toolbox for MATLAB. Technical report. http://www.mathworks.com/support/ftp/
  17. 54.
    R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters (Wiley, Hoboken, 2005) Google Scholar
  18. 57.
    S. Ouzounov, E. Roza, H. Hegt, G. van der Weide, A. van Roermund, An 8 MHz, 72 dB SFDR asynchronous sigma-delta modulator with 1.5 mW power dissipation, in Proceedings 2004 Symp. VLSI Circuits (2004), pp. 88–91 Google Scholar
  19. 58.
    S. Ouzounov, H. Hegt, A. van Roermund, Sigma-delta modulators operating at a limit cycle. IEEE Trans. Circuits Syst. II 53(5), 399–403 (2006) CrossRefGoogle Scholar
  20. 59.
    S. Ouzounov, R. Veldhoven, C. Bastiaansen, K. Vongehr, R. Wegberg, G. Geelen, L. Breems, A. Roermund, A 1.2 V 121-mode CT ΔΣ modulator for wireless receivers 90 nm CMOS, in IEEE ISSCC Proceedings (2007), p. 242 Google Scholar
  21. 60.
    S. Paton, Contribución al modelado y diseño de modulatores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia (English Summary). Technical report, Universidad Carlos III de Madrid, 2004; PhD thesis, Madrid, Spain Google Scholar
  22. 61.
    S. Paton, A. Giandomenico, L. Hernandez, A. Wiesbauer, Th. Poetscher, M. Clara, A 70-mW 300-MHz CMOS continuous-time sigma-delta ADC with 15-MHz bandwidth and 11 bits of resolution. IEEE J. Solid-State Circuits 39(7), 1056–1063 (2004) CrossRefGoogle Scholar
  23. 63.
    St. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, D. Schmitt-Landsiedel, A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion. IEEE J. Solid-State Circuits 43(7), 1666–1676 (2008) CrossRefGoogle Scholar
  24. 71.
    W. Sansen, Analog Design Essentials (Springer, Dordrecht, 2006) Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Richard Gaggl
    • 1
  1. 1.Design Center VillachInfineon TechnologiesVillachAustria

Personalised recommendations