A Delta-Sigma Converter with Dynamic-Biasing Technique

  • Richard Gaggl
Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 39)


A high-resolution multi-bit Delta-Sigma ADC implemented in a 0.18 μm CMOS technology is introduced [47]. The circuit is targeted for an ADSL Central-Office application. An area- and power-efficient realization of a single-loop modulator consisting of a 2nd-order loopfilter and a 3-bit quantizer with an oversampling-ratio of 96 is presented. The delta-sigma modulator features an 85 dB dynamic-range (DR) over a 300 kHz signal bandwidth. The measured power consumption of the ADC core is 15 mW only. An innovative biasing circuitry is introduced for the switched-capacitor integrators. The FOM taking the DR as reference ( 2.7) results in \(1.8~\frac{\mathrm{pJ}}{\mathrm{conv}}\).


Noise Transfer Function Asymmetric Digital Subscriber Line Signal Transfer Function Sampling Capacitor Dynamic Element Match 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Richard Gaggl
    • 1
  1. 1.Design Center VillachInfineon TechnologiesVillachAustria

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