Abstract
Real-time face detection is important in human-computer interaction. A new FPGA-based parallel hardware architecture is proposed here. The Pareto Principle is used in the architecture to analyze the distribution of sub-window, showing that sub-windows with higher strong classifier information are concentrated and only a tiny part; the jumping scanning mechanism is designed to improve detection speed. In addition, sub-windows using line ram array effectively reduce the usage of on-chip memory, and achieve the same read speed of register array. The hardware architecture of face-detection is implemented and verified on Stratix IV; compared with the same computing resource, real-time face detection processing is realized at speed increased by 27%.
This work is supported partly by key projects in the science & technology pillar program of Tianjin, P.R. China. (No. 10ZCKFGX01100).
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Viola, P., Jones, M.J.: Robust Real-Time Face Detection. International Journal of Computer Vision 57(2), 137–154 (2004)
Yang, M., Crenshaw, J., Augustine, B., Mareachen, R., Wu, Y.: Face detection for automatic exposure control in handheld camera. In: Fourth IEEE International Conference on Computer Vision Systems (2006)
Yang, M., Crenshaw, J., Augustine, B., Mareachen, R., Wu, Y.: AdaBoost-based face detection for embedded systems. Computer Vision and Image Understanding (2010)
Lai, H.-C., Savvides, M., Chen, T.: Proposed FPGA Hardware Architecture for High Frame Rate (>100fps) Face Detection Using Feature Cascade Classifiers. In: IEEE Conference on Biometrics: Theory, Applications and Systems (2007)
Kim, J.-S., Lee, H.J.: A Novel Architecture for Low Bandwidth and High Utilization in Face Detection with Haar-like Features (2011)
Hiromoto, M., Nakahara, K., Sugano, H.: A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features (2007)
Hiromoto, M., Nakahara, K., Sugano, H.: Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features. IEEE Transactions on Circuits and Systems for Video Technology 19(1) (January 2009)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Qin, C., Che, M., Li, W. (2012). A Novel Architecture on FPGA for Face Detection Using Jumping Scanning Mechanism. In: Khachidze, V., Wang, T., Siddiqui, S., Liu, V., Cappuccio, S., Lim, A. (eds) Contemporary Research on E-business Technology and Strategy. iCETS 2012. Communications in Computer and Information Science, vol 332. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34447-3_15
Download citation
DOI: https://doi.org/10.1007/978-3-642-34447-3_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-34446-6
Online ISBN: 978-3-642-34447-3
eBook Packages: Computer ScienceComputer Science (R0)