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International Conference on Security, Privacy, and Applied Cryptography Engineering

SPACE 2012: Security, Privacy, and Applied Cryptography Engineering pp 1–15Cite as

A Novel Circuit Design Methodology to Reduce Side Channel Leakage

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Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 7644))

Abstract

To estimate the probable information leakage of a logic circuit through a side channel is a major problem for circuit designers. In this paper a novel circuit design methodology is presented to estimate and reduce the side channel leakage of logic gates. The focus lies on the investigation of side channel leakage during circuit design. With this novel methodology three different logic circuit families are compared. Additionally, the process of improving a logic circuit using this methodology is shown in detail.

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Author information

Authors and Affiliations

  1. Analogue Integrated Circuits Research Group, Ruhr-Universität Bochum, Universitätsstraße 150, 44780, Bochum, Germany

    Andreas Gornik, Ivan Stoychev & Jürgen Oehm

Authors
  1. Andreas Gornik
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  2. Ivan Stoychev
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  3. Jürgen Oehm
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Editor information

Editors and Affiliations

  1. ESAT/SCD/COSIC, KU Leuven, Kasteelpart Arenberg 10, 3001, Leuven-Heverlee, Belgium

    Andrey Bogdanov

  2. IIIT Delhi, Okhla Industrial Area, Phase III, 110020, New Delhi, India

    Somitra Sanadhya

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© 2012 Springer-Verlag Berlin Heidelberg

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Gornik, A., Stoychev, I., Oehm, J. (2012). A Novel Circuit Design Methodology to Reduce Side Channel Leakage. In: Bogdanov, A., Sanadhya, S. (eds) Security, Privacy, and Applied Cryptography Engineering. SPACE 2012. Lecture Notes in Computer Science, vol 7644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34416-9_1

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  • DOI: https://doi.org/10.1007/978-3-642-34416-9_1

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-34415-2

  • Online ISBN: 978-3-642-34416-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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