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A Novel Circuit Design Methodology to Reduce Side Channel Leakage

  • Andreas Gornik
  • Ivan Stoychev
  • Jürgen Oehm
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7644)

Abstract

To estimate the probable information leakage of a logic circuit through a side channel is a major problem for circuit designers. In this paper a novel circuit design methodology is presented to estimate and reduce the side channel leakage of logic gates. The focus lies on the investigation of side channel leakage during circuit design. With this novel methodology three different logic circuit families are compared. Additionally, the process of improving a logic circuit using this methodology is shown in detail.

Keywords

circuit design DPA countermeasures side channel leakage 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Andreas Gornik
    • 1
  • Ivan Stoychev
    • 1
  • Jürgen Oehm
    • 1
  1. 1.Analogue Integrated Circuits Research GroupRuhr-Universität BochumBochumGermany

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