HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware

Abstract

Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In this paper we present HAVEN, a freely available open functional verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification runs. HAVEN takes advantage of the inherent parallelism of hardware systems and moves the verified system together with transaction-based interface components of the functional verification environment from software into an FPGA. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM), assertion-based verification, and also provides adequate debugging visibility, making its application range quite large. Our experiments confirm the assumption that the achieved acceleration is proportional to the complexity of the verified system, with the peak acceleration ratio being over 1,000.

This work was supported by the Czech Science Foundation (projects P103/10/0306 and 102/09/1668), the Czech Ministry of Education (projects COST OC10009 and MSM 0021630528), Reduced Certification Costs Using Trusted Multi-core Platforms project, Artemis JU, RECOMP #100202 and the BUT FIT project FIT-S-11-1. An extended version of this paper is available as the technical report [1].