Advertisement

Injecting Floating-Point Testing Knowledge into Test Generators

  • Merav Aharony
  • Emanuel Gofman
  • Elena Guralnik
  • Anatoly Koyfman
Conference paper
  • 721 Downloads
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7261)

Abstract

Floating-point unit (FPU) verification is a known challenge, due to the variety of corner cases both in its data path and control flow. We have identified a gap in the coverage of FP corner cases that combine special data and control scenarios. We propose a solution based on combining the deep FP knowledge of a special FP test generator with the strength of a general-purpose test generator. We present a novel FP testing knowledge package (FPTK) that consists of a weighted set of FP scenarios. We explain the flow of combining the existing tools with the FPTK and demonstrate its effect.

Keywords

Test Generator Very Large Scale Integration Corner Case Test Template Test Generation Process 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Nelson, H.F.: Beebe’s IEEE754 Floating-Point test software, http://www.math.utah.edu/~beebe/software/ieee
  2. [2]
    Floating-Point Test Suite for IEEE 754R Standard, https://www.research.ibm.com/haifa/projects/verification/fpgen/ieeets.html
  3. [3]
    Aharon, A., Goodman, D., Levinger, M., Lichtenstein, Y., Malka, Y., Metzger, C., Molho, M., Shurek, G.: Test Program Generation for Functional Verification of PowerPC Processors in IBM. In: Proceedings of the 32th Design Automation Conference, pp. 279–285 (1995)Google Scholar
  4. [4]
    Arbetman, Y., Levinger, M., Fournier, L.: Functional Verification Methodology of Microprocessors Using the Genesys Test Program Generator. Application to the x86 Microprocessors Family. In: Proceedings of the Design, Automation, and Test in Europe (DATE 1999), pp. 434–441 (1999)Google Scholar
  5. [5]
    Naveh, Y., Rimon, M., Jaeger, I., Katz, Y., Vinov, M., Marcus, E., Shurek, G.: Constraint-biased Random Stimuli Generation for Hardware Verification. AI Magazine 28(2), 13–30 (2007)Google Scholar
  6. [6]
    Chandra, A., Iyengar, V., Jameson, D., Jawalekar, R., Nair, I., Rosen, B., Mullen, M., Yoon, J., Armoni, R., Geist, D., Wolfsthal, Y.: AVPGEN - a test generator for architecture verification. IEEE Transaction on Very Large Scale Integration (VLSI) Systems 3(2), 157–172 (1995)CrossRefGoogle Scholar
  7. [7]
    Aharoni, M., Asaf, S., Fournier, L., Koyfman, A., Nagel, R.: FPgen - A Test Generation Framework for Datapath Floating-Point Verification. In: Proc. IEEE International High Level Design Validation and Test Workshop 2003, HLDVT 2003 (2003)Google Scholar
  8. [8]
    Parks, M.: Number-theoretic Test Generation for Directed Rounding. In: Proc. Computer Arithmetic, pp. 241–248 (1999)Google Scholar
  9. [9]
    Kahan, W.: A test for Correctly Rouned SQRT, http://www.eecs.berkeley.edu/~wkahan/SQRT.ps
  10. [10]
    McFearin, L., Matula, D.: Generation and Analisys of Hard to Round Cases for Binary FP Division. In: Proc. Computer Arithmetic, pp. 119–126 (2001)Google Scholar
  11. [11]
    Rimon, M., Lichtenstein, Y., Adir, A., Jaeger, I., Vinov, M., Johnson, S., Jani, D.: Addressing Test Generation Challenges for Configurable Processor Verification. In: 2006 IEEE International High-Level Design Validation and Test Workshop (2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Merav Aharony
    • 1
  • Emanuel Gofman
    • 1
  • Elena Guralnik
    • 1
  • Anatoly Koyfman
    • 1
  1. 1.IBM Research LaboratoryHaifaIsrael

Personalised recommendations