Abstract
In this paper both theoretical and experimental comparative performance analysis of several binary adder architectures is performed. Also, one modified carry-bypass technique for adder performance improvement is presented. When applying simple unit-gate theoretical model for area and delay estimation it has been shown that logarithmic delay architectures (carry-lookahead and prefix adders) are the fastest but the most hardware demanding. On the other hand, the implementations in modern Virtex-6 general purpose FPGAs witness that here presented carry-bypass technique is the best tradeoff for such devices in terms of area, speed and power consumption. Presented results can be considered as a valuable resource in the selection of the most appropriate adder topology that will be used to implement a given arithmetic operation in a specified technology.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Fang, C., Huang, C., Wang, J., Yeh, C.: Fast and compact dynamic ripple carry adder design. In: IEEE Asia-Pacific Conf. on ASIC, pp. 25–28 (2002)
Bedrij, O.: Carry-select adder. IRE Trans. Electron. Comput. 11, 340–346 (1962)
Alioto, M., Palumbo, G.: Optimized design of carry-bypass adders. In: European Conf. on Circuit Theory and Design, pp. 245–248 (2001)
Chen, J.: Parallel-prefix structures for binary and modulo {2n-1,2n,2n+1} adders. PhD thesis, Oklahoma State University (2008)
Zimmermann, R.: Binary adder architectures for cell-based VLSI and their synthesis. PhD thesis, Swiss Federal Institute of Technology (1997)
Tyagi, A.: A reduced area scheme for carry-select adders. IEEE Trans. Comput. 42, 1162–1170 (1993)
Xilinx Inc., Virtex-6 FPGA data sheet: DC and Switching Characteristics, v3.4 edition (2012)
Jose, B., Radhakrishnan, D.: Delay optimized redundant binary adders. In: Int. Conf. on Electronics, Circuits and Systems, pp. 514–517 (2006)
Shams, A., Darwish, T., Bayoumi, M.: Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans. on VLSI Systems. 10, 20–29 (2002)
Chang, C., Gu, J., Zhang, M.: A Review of 0.18 /spl mu/ m full adder performances for tree structured arithmetic circuits. IEEE Trans. on VLSI Systems 13, 686–695 (2005)
Alioto, M., Cataldo, G.D., Palumbo, G.: Mixed full adder topologies for high-performance low-power arithmetic circuits. Microelectronics Journal 38, 130–139 (2007)
Amelifard, B., Fallah, F., Pedram, M.: Closing the gap between carry select adder and ripple carry adder: a new class of low-power high performance adders. In: Int. Symp. on Quality of Electronic Design, pp. 148–152 (2005)
Knowles, S.: A family of adders. In: 15th IEEE Symp. on Computer Arithmetic, pp. 277–281 (2001)
Kharbash, F.: Redundant adder architectures, PhD Thesis, University of Missouri (2011)
Patil, D., Azizi, O., Horowitz, M., Ho, R.: Robust energy-efficient adder Topologies. In: 18th IEEE Symp. on Computer Arithmetic, pp. 16–28 (2007)
Shanzen, X., Yu, W.: FPGA adders: performance evaluation and optimal design. IEEE Design&Test of Computers 15, 24–29 (1998)
Dinechin, F., Nguyen, H., Pasca, B.: Pipelined FPGA adders. In: Int. Conf. on Field Programmable Logic, pp. 422–427 (2010)
Nguyen, H., Pasca, B., Preusser, T.: FPGA-specific arithmetic optimizations of short-latency adders. In: Int. Conf. on Field Programmable Logic, pp. 232–237 (2011)
Oklobdzija, V., Barnes, E.: Some optimal schemes for ALU implementation in VLSI technology. In: Proc. of the 7th Symposium on Comp. Arith., pp. 2–8 (1985)
Sklansky, J.: Conditional sum addition logic. IRE Trans. on Electronic Computers 9, 226–231 (1960)
Jadhov, S.: Advanced computer arithmetic and computing. Technical Publications Pune (2009)
XPower Analyzer tutorial, ftp://ftp.xilinx.com/pub/documentation/tutorials/xpowerfpgatutorial.pdf
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Jovanović, B., Jevtić, M. (2013). Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs. In: Balas, V., Fodor, J., Várkonyi-Kóczy, A., Dombi, J., Jain, L. (eds) Soft Computing Applications. Advances in Intelligent Systems and Computing, vol 195. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33941-7_27
Download citation
DOI: https://doi.org/10.1007/978-3-642-33941-7_27
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-33940-0
Online ISBN: 978-3-642-33941-7
eBook Packages: EngineeringEngineering (R0)