Abstract
Many multi-core processors exhibit characteristics that make it difficult or even impossible to use them in safety-critical real-time systems. To prevent sporadic failures and late-stage integration problems, the hardware properties of the processor and its peripherals have to be checked for their real-time capability at an early project stage. Selecting a configuration which enables predictable performance is an important requirement to achieve compliance with current safety standards, e.g., ISO-26262, IEC-61508, EN-50128, or DO-178B.
For timing-predictable hardware configurations safe worst-case execution time bounds can be computed by static analysis tools. Combined with scheduling analysis at the system level the correct end-to-end timing can be guaranteed. This article gives an overview of hardware features leading to predictability problems, shows examples of predictability-oriented multi-core configurations, and describes a tool-based methodology to ensure the correct timing behavior.
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Kästner, D. et al. (2012). Meeting Real-Time Requirements with Multi-core Processors. In: Ortmeier, F., Daniel, P. (eds) Computer Safety, Reliability, and Security. SAFECOMP 2012. Lecture Notes in Computer Science, vol 7613. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33675-1_10
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DOI: https://doi.org/10.1007/978-3-642-33675-1_10
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