DNA-Inspired Scheme for Building the Energy Profile of HPC Systems

  • Ghislain Landry Tsafack Chetsa
  • Laurent Lefevre
  • Jean-Marc Pierson
  • Patricia Stolf
  • Georges Da Costa
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7396)


Energy usage is becoming a challenge for the design of next generation large scale distributed systems. This paper explores an innovative approach of profiling such systems. It proposes a DNA-like solution without making any assumptions on the running applications and used hardware. This profiling based on internal counters usage and energy monitoring allows to isolate specific phases during the execution and enables some energy consumption control and energy usage prediction. First experimental validations of the system modeling are presented and analyzed.


Performance Counter Power Consumption Estimation Monitoring Counter System Energy Consumption Hardware Counter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Annavaram, M., Grochowski, E., Shen, J.P.: Mitigating amdahl’s law through epi throttling. In: ISCA, pp. 298–309. IEEE Computer Society (2005)Google Scholar
  2. 2.
    Bailey, D.H., Barszcz, E., Barton, J.T., Carter, R.L., Lasinski, T.A., Browning, D.S., Dagum, L., Fatoohi, R.A., Frederickson, P.O., Schreiber, R.S.: The nas parallel benchmarks. International Journal of High Performance Computing Applications 5, 63–73 (1991)CrossRefGoogle Scholar
  3. 3.
    Bautista, D., Sahuquillo, J., Hassan, H., Petit, S., Duato, J.: A simple power-aware scheduling for multicore systems when running real-time applications. In: IPDPS, pp. 1–7. IEEE (2008)Google Scholar
  4. 4.
    Contreras, G.: Power prediction for intel xscale processors using performance monitoring unit events. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), pp. 221–226. ACM Press (2005)Google Scholar
  5. 5.
    Costa, G.D., Hlavacs, H.: Methodology of measurement for energy consumption of applications. In: GRID, pp. 290–297. IEEE (2010)Google Scholar
  6. 6.
    Curtis-Maury, M., Dzierwa, J., Antonopoulos, C.D., Nikolopoulos, D.S.: Online power-performance adaptation of multithreaded programs using hardware event-based prediction. In: Egan, G.K., Muraoka, Y. (eds.) ICS, pp. 157–166. ACM (2006)Google Scholar
  7. 7.
    Dhodapkar, A.S., Smith, J.E.: Managing multi-configurable hardware via dynamic working set analysis. In: 29th Annual International Symposium on Computer Architecture, pp. 233–244 (2002)Google Scholar
  8. 8.
    Freeh, V.W., Kappiah, N., Lowenthal, D.K., Bletsch, T.K.: Just-in-time dynamic voltage scaling: Exploiting inter-node slack to save energy in mpi programs. J. Parallel Distrib. Comput. 68(9), 1175–1185 (2008)CrossRefGoogle Scholar
  9. 9.
    Ge, R., Feng, X., Cameron, K.W.: Performance-constrained distributed dvs scheduling for scientific applications on power-aware clusters. In: Proceedings of the 2005 ACM/IEEE conference on Supercomputing, SC 2005, p. 34. IEEE Computer Society, Washington, DC (2005)Google Scholar
  10. 10.
    Joseph, R., Martonosi, M.: Run-time power estimation in high performance microprocessors. In: International Symposium on Low Power Electronics and Design, pp. 135–140 (2001)Google Scholar
  11. 11.
    Kadayif, I., Chinoda, T., Kandemir, M., Vijaykirsnan, N., Irwin, M.J., Sivasubramaniam, A.: vec: virtual energy counters. In: Proceedings of the 2001 ACM SIGPLAN-SIGSOFT Workshop on Program Analysis for Software Tools and Engineering, PASTE 2001, pp. 28–31. ACM, New York (2001)CrossRefGoogle Scholar
  12. 12.
    Kansal, A., Zhao, F.: Fine-grained energy profiling for power-aware application design. SIGMETRICS Perform. Eval. Rev. 36, 26–31 (2008)CrossRefGoogle Scholar
  13. 13.
    Kimura, H., Imada, T., Sato, M.: Runtime energy adaptation with low-impact instrumented code in a power-scalable cluster system. In: Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing, CCGRID 2010, pp. 378–387. IEEE Computer Society, Washington, DC (2010)CrossRefGoogle Scholar
  14. 14.
    Lim, M.Y., Freeh, V.W., Lowenthal, D.K.: Adaptive, transparent frequency and voltage scaling of communication phases in mpi programs. In: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, SC 2006. ACM, New York (2006)Google Scholar
  15. 15.
    Lively, C., Wu, X., Taylor, V., Moore, S., Chang, H.-C., Su, C.-Y., Cameron, K.: Power-aware predictive models of hybrid (MPI/OpenMP) scientific applications on multicore systems. In: Computer Science - Research and Development, pp. 1–9 (August 2011)Google Scholar
  16. 16.
    Singh, K., Bhadauria, M., McKee, S.A.: Real time power estimation and thread scheduling via performance counters. SIGARCH Comput. Archit. News 37, 46–55 (2009)CrossRefGoogle Scholar
  17. 17.
    Weissel, A., Bellosa, F.: Process cruise control-event-driven clock scaling for dynamic power management. In: Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2002), Grenoble, France (2002)Google Scholar
  18. 18.
    Wu, W., Jin, L., Yang, J., Liu, P., Tan, S.X.D.: A systematic method for functional unit power estimation in microprocessors. In: Design Automation Conference (2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Ghislain Landry Tsafack Chetsa
    • 1
    • 2
  • Laurent Lefevre
    • 1
  • Jean-Marc Pierson
    • 2
  • Patricia Stolf
    • 2
  • Georges Da Costa
    • 2
  1. 1.INRIA, LIP Laboratory (UMR CNRS, ENS, INRIA, UCB)Ecole Normale Superieure de Lyon, Université de LyonFrance
  2. 2.IRIT (UMR CNRS)University of ToulouseToulouse CEDEX 9France

Personalised recommendations