Abstract
The major challenge for the semiconductor industry is to design devices in short time with complex logical functionality. At the very top of the list of challenges to be solved is verification. The goal of the verification is to ensure that the design meets the logical functional requirements as defined in the logical functional specification. Verification of the devices takes 40 to 70 per cent of the total development effort for the design. The increasing complexity of hardware designs raises the need for the development of new techniques and methodologies that can provide the verification team with the means to achieve its goals quickly and with limited resources.
We present a framework that enables verification test generation using circuit model presented in VHDL hardware description language. The framework consists of several tools. We use the third party tool VSYML for VHDL description translation. Our tool then extracts finite state machine (FSM) model from translated VHDL description. The goal of the model is to use it for verification test generation. We introduce our software tool and algorithm, as well. The experimental results are presented for the benchmark suite ITC’99. The obtained results demonstrated the viability of the framework.
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References
Bareisa, E., Jusas, V., Motiejunas, K., Seinauskas, R.: The Use of a Software Prototype for Verification Test Generation. Inf. Technol. Control 37(4), 265–274 (2008)
Lam, W.K.: Hardware Design Verification: Simulation and Formal Method-Based Approaches. Prentice Hall PTR (2005)
Lichtenstein, Y., Malka, Y., Aharon, A.: Model-Based Test Generation for Processor Design Verification. In: Proceedings of the Sixth Innovative Applications of Artificial Intelligence (IAAI) Conference, pp. 83–94. AAAI Press (1994)
Fournier, L., Arbetman, Y., Levinger, M.: Functional verification methodology for microprocessors using the Genesys test-program generator. In: Proceedings of the Conference on Design, Automation and Test in Europe, Munich, Germany. ACM (1999)
Fine, S., Ziv, A.: Coverage directed test generation for functional verification using Bayesian networks (2003)
Tun, L., Dan, Z., Yang, G., GongJie, L., SiKun, L.: MA2TG: a functional test program generator for microprocessor verification (2005)
Bhaskar, K.U., Prasanth, M., Kamakoti, V., Maneparambil, K.: A Framework for Automatic Assembly Program Generator (A^2PG) for Verification and Testing of Processor Cores (2005)
Behm, M., Ludden, J., Lichtenstein, Y., Rimon, M., Vinov, M.: Industrial experience with test generation languages for processor verification. In: Proceedings of the 41st Annual Design Automation Conference, San Diego, CA, USA. ACM (2004)
Al-Asaad, H., Hayes, J.P.: Design verification via simulation and automatic test pattern generation. In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, United States. IEEE Computer Society (1995)
Ugarte, I., Sanchez, P.: Functional vector generation for assertion-based verification at behavioral level using interval analysis. In: Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop. IEEE Computer Society (2003)
Tung, S.-W., Jou, J.-Y.: Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. In: Proceedings of the 7th Asian Test Symposium. IEEE Computer Society (1998)
Moundanos, D., Abraham, J.A.: 12.1 Using Verification Technology for Validation Coverage Analysis and Test Generation. In: Proceedings of the 16th IEEE VLSI Test Symposium. IEEE Computer Society (1998)
Cheng, K.T., Krishnakumar, A.S.: Automatic functional test generation using the extended finite state machine model. In: Proceedings of the 30th International Design Automation Conference, Dallas, Texas, United States. ACM (1993)
IEEE Standards Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual. IEEE Std 1076/INT-19911, 1 (992)
IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999) 0_1-112 (2004)
Barnes, J.: Ada 95 Rationale: The Language, the Standard Libraries. Springer (1995)
Maksoud, M.A., Pister, M., Schlickling, M.: An abstraction-aware compiler for VHDL models (2009)
Ouchet, F., Borrione, D., Morin-Allory, K., Pierre, L.: High-level symbolic simulation for automatic model extraction (2009)
Carter, W.C., Joyner Jr., W.H., Brand, D.: Symbolic Simulation for Correct Machine Design (1979)
Bryant, R.E.: Symbolic simulation-techniques and applications (1990)
Cadar, C., Godefroid, P., Khurshid, S., Pasareanu, C.S., Sen, K., Tillmann, N., Visser, W.: Symbolic execution for software testing in practice: preliminary assessment (2011)
Johnson, D.B.: Finding All the Elementary Circuits of a Directed Graph. SIAM Journal on Computing 4(1), 77–84 (1975)
Corno, F., Reorda, M.S., Squillero, G.: RT-level ITC’99 benchmarks and first ATPG results. IEEE Design & Test of Computers 17(3), 44–53 (2000)
Bjrner, N.: SMT Solvers for Testing, Program Analysis and Verification at Microsoft (2009)
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Jusas, V., Neverdauskas, T. (2012). FSM Based Functional Test Generation Framework for VHDL. In: Skersys, T., Butleris, R., Butkiene, R. (eds) Information and Software Technologies. ICIST 2012. Communications in Computer and Information Science, vol 319. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33308-8_12
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DOI: https://doi.org/10.1007/978-3-642-33308-8_12
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