Hardware/Software Co-design for Real Time Embedded Image Processing: A Case Study

  • Sol Pedre
  • Tomáš Krajník
  • Elías Todorovich
  • Patricia Borensztejn
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7441)


Many image processing applications need real time performance, while having restrictions of size, weight and power consumption. These include a wide range of embedded systems from remote sensing applications to mobile phones. FPGA-based solutions are common for these applications, their main drawback being long development time. In this work a co-design methodology for processor-centric embedded systems with hardware acceleration using FPGAs is applied to an image processing method for localization of multiple robots. The goal of the methodology is to achieve a real-time embedded solution using hardware acceleration, but with development time similar to software projects. The final embedded co-designed solution processes 1600×1200 pixel images at a rate of 25 fps, achieving a 12.6× acceleration from the original software solution. This solution runs with a comparable speed as up-to-date PC-based systems, and it is smaller, cheaper and demands less power.


real time image processing hardware/software co-design methodology FPGA robotics 


  1. 1.
    NVIDIA: CUDA: Parallel Programming (January 2012),
  2. 2.
    Jošth, R., et al.: Real-time PCA calculation for spectral imaging (using SIMD and GP-GPU). Journal of Real-Time Image Processing, 1–9 (2012)Google Scholar
  3. 3.
    Cornelis, N., van Gool, L.: Fast scale invariant feature detection and matching on programmable graphics hardware. In: IEEE International Conference on Computer Vision and Pattern Recognition, CVPR, Anchorage Alaska (June 2008)Google Scholar
  4. 4.
    Diaz, J., et al.: FPGA-based real-time optical-flow system. IEEE Transactions on Circuits and Systems for Video Technology 16(2), 274–279 (2006)CrossRefGoogle Scholar
  5. 5.
    Pedre, S., Stoliar, A., Borensztejn, P.: Real Time Hot Spot Detection using FPGA. In: 14th Iberoamerican Congress on Pattern Recognition, pp. 595–602. Springer (2009)Google Scholar
  6. 6.
    Bonato, V., Marques, E., Constantinides, G.A.: A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection. Transactions on Circuits and Systems for Video Technology 18(12), 1703–1712 (2008)CrossRefGoogle Scholar
  7. 7.
    Jordan, H., Dyck, W., Smodic, R.: A co-processed contour tracing algorithm for a smart camera. Journal of RealTime Image Processing 6(1), 23–31 (2010)CrossRefGoogle Scholar
  8. 8.
    Castillo, A., Shkvarko, Y., Torres Roman, D., Perez Meana, H.: Convex regularization based hardware/software co-design for real-time enhancement of remote sensing imagery. Journal of Real-Time Image Processing 4, 261–272 (2009)CrossRefGoogle Scholar
  9. 9.
    Bailey, B., Martin, G., Piziali, A.: ESL Design and Verification: A prescription for Electronic System-Level Methodology. Morgan Kaufmann (2007)Google Scholar
  10. 10.
    Pedre, S., Krajník, T., Todorovich, E., Borensztejn, P.: A co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA. In: IEEE 8th Southern Programmable Logic Conference, pp. 7–14. IEEE, Brazil (2012)Google Scholar
  11. 11.
    Mallet, F., André, C., DeAntoni, J.: Executing AADL Models with UML/MARTE. In: International Conference of Engineering of Complex Computer Systems, pp. 371–376. IEEE, Germany (2009)CrossRefGoogle Scholar
  12. 12.
    Mueller, W., Rosti, A., Bocchio, S., Riccobene, E., Scandurra, P., Dehaene, W., Vanderperren, Y., Ku, L.: UML for ESL Design - Basic Principles, Tools, and Applications. In: IEEE/ACM Int. Conf. on Computer Aided Design, pp. 73–80 (November 2006)Google Scholar
  13. 13.
    Silva-Filho, A.G., et al.: An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms. International Journal of Reconfigurable Computing, 1–12 (2011)Google Scholar
  14. 14.
    Jacquard: ROCCC 2.0 (October 2011),
  15. 15.
    Mentor-Graphics: CatapultC (October 2011),
  16. 16.
    Nallatech: DIME-C (October 2011),
  17. 17.
    Gaisler, J.: A structured VHDL design method. In: Fault-tolerant Microprocessors for Space Applications. Gaisler Research, pp. 41–50 (2004)Google Scholar
  18. 18.
    ESA: European Space Agency VHDL (October 2011),
  19. 19.
    Kulich, M., et al.: SyRoTek - On an e-Learning System for Mobile Robotics and Artificial Intelligence. In: ICAART 2009, pp. 275–280. INSTICC Press, Setúbal (2009)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Sol Pedre
    • 1
  • Tomáš Krajník
    • 2
  • Elías Todorovich
    • 3
  • Patricia Borensztejn
    • 1
  1. 1.Departamento de ComputaciónFCEN-UBAArgentina
  2. 2.Czech Technical University in PragueCzech Republic
  3. 3.Departamento de Computación y SistemasFCE-UNICENArgentina

Personalised recommendations