Abstract
This chapter presents the methods used by the placer to process and place the modules in the floorplan while following the designer guidelines embedded in the template. The general architecture of the placer is addressed followed by the description of the high level guidelines present in the template. Finally, the detailed generation procedure for the floorplan, depicting each task implemented in LAYGEN II’s template-based placer is presented.
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References
Y.-C. Chang, Y.-W. Chang, G.-M.Wu, S.-W.Wu, B*-trees: a new representation for nonslicing floorplans, in Proceedings of 37th ACM/IEEE Design Automation Conference (DAC), pp. 458–463 (2000)
F. Balasa, S. C. Maruvada, K. Krishnamoorthy, Using red-black interval trees in device-level analog placement with symmetry constraints, in Proceedings of the Asian and South Pacific—Design Automation Conference (ASPDAC), pp. 777–782 (January 2003)
N. Lourenço, M. Vianello, J. Guilherme, N. Horta, LAYGEN—automatic layout generation of analog ICs from hierarchical template descriptions, in Proceedings of the Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 213–216 (June 2006)
B. Suman, P. Kumar, A survey of simulated annealing as a tool for single and multiobjective optimization. J. Oper. Res. Soc. 57, 1143–1160 (2006)
R. Jacob Baker, CMOS Circuit Design, Layout and Simulation (IEEE Press, New York, 2005)
M. Barros, J. Guilherme, N. Horta, GA-SVM feasibility model and optimization kernel applied to analog IC design automation, in Proceedings of ACM Great Lakes symposium on VLSI (GLVLSI), pp. 469–472 (March 2007)
M. Barros, J. Guilherme, N. Horta, Analog circuits and systems optimization based on evolutionary computation techniques, Studies in computational intelligence, vol. 294 (Springer, New York 2010)
M. Barros, J. Guilherme, N. Horta, Analog circuits optimization based on evolutionary computation techniques. Integration, VLSI J. 43(1), 136–155 (2009)
N. Lourenço, N. Horta, GENOM-POF: multi-objective evolutionary synthesis of analog ICs with Corners validation, in Proceedings of Genetic and Evolutionary Computation Conference (GECCO), (July 2012)
F. Maloberti, Analog Design for CMOS VLSI Systems, (Kluwer Academic Publishers, Netherlands 2001)
A. Hastings, The Art of Analog Layout, 2nd edn (Prentice Hall, New Jersey 2005)
Mentor Graphics, http://www.mentor.com
R.L. Graham, An efficient algorithm for determining the convex hull of a finite planar set. Inform Proc. Lett. 1, 132–133 (1972)
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Martins, R.M.F., Lourenço, N.C.C., Horta, N.C.G. (2013). Placer. In: Generating Analog IC Layouts with LAYGEN II. SpringerBriefs in Applied Sciences and Technology(). Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33146-6_4
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DOI: https://doi.org/10.1007/978-3-642-33146-6_4
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