Abstract
Hardware-Software partitioning and scheduling are the crucial steps in HW-SW codesign of MPSoC since they have a strong effect on the performance, area, power and the system. Considered as NP-complete problem, the involvement of inter-task data dependencies have posed a serious challenge on the MPSoC based embedded application domain. In this paper, we propose an efficient algorithm for dependent task HW-SW codesign with Greedy Partitioning and Insert Scheduling Method (GPISM) by task graph. For hardware tasks, the critical path with maximum sum of benefit-to-area ratio can be achieved and implemented in hardware while the total area occupation in this path fitting global hardware constraint; after that, the task graph is updated by removing tasks in the critical path iteratively until the available hardware area doesn’t fit. For software tasks, the longest communication time path can be obtained from the updated task graph and assigned to software implementation integrally, then second path will be located if it does exist. For task scheduling, rest scatter nodes are inserted into hardware/software implementation list by scheduling criterion. Simulation results demonstrate that GPISM algorithm has a polynomial time complexity without affordable computation; meanwhile it can greatly improve system performance even in the case of generation large communication cost, and efficiently facilitate the researchers to partition and schedule embedded applications on MPSoC hardware architectures.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Garey, M.R., Johnson, D.S.: Computers and intractability: a guide to the theory of NP-completeness. W.H. Freeman (1979)
Graham, R.L.: Bounds on multiprocessing timing anomalies. SIAM Journal on Applied Mathematics 17, 416–429 (1969)
Wu, J., Srikanthan, T., Guang, C.: Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms. IEEE Transactions on Computers 59(4), 532–544 (2010)
Youness, H., et al.: A high performance algorithm for scheduling and hardware-software partitioning on MPSoCs. In: 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, DTIS 2009 (2009)
Youness, H., et al.: Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. In: Proceedings of 2010 IEEE International Symposium on Circuits and Systems, ISCAS (2010)
Vahid, F., Gajski, D.D.: Clustering for improved system-level functional partitioning. In: Proceedings of the Eighth International Symposium on System Synthesis (1995)
Niemann, R., Marwedel, P.: Hardware/software partitioning using integer programming. In: Proceedings of European Design and Test Conference, ED&TC 1996 (1996)
Wu, J., Srikanthan, T.: Low-complex dynamic programming algorithm for hardware/software partitioning. Information Processing Letters 98(2), 41–46 (2006)
Shiann-Rong, K., Chin-Yang, C., Ren-Zheng, L.: Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming. In: Proceedings of 11th International Conference on Parallel and Distributed Systems (2005)
Chatha, K.S., Vemuri, R.: Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(3), 193–208 (2002)
Yi, Z., Zhenquan, Z., Huanhuan, C.: HW-SW partitioning based on genetic algorithm. In: Congress on Evolutionary Computation, CEC 2004 (2004)
Lanying, L., Yanbo, S., Ming, G.: A new genetic simulated annealing algorithm for hardware-software partitioning. In: 2010 2nd International Conference on Information Science and Engineering, ICISE (2010)
Lanying, L., Min, S.: Software-Hardware Partitioning Strategy Using Hybrid Genetic and Tabu Search. In: International Conference on Computer Science and Software Engineering (2008)
Chatha, K.S., Vemurl, R.: MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001 (2001)
Le-jun, F., et al.: An Approach for Dynamic Hardware /Software Partitioning Based on DPBIL. In: Third International Conference on Natural Computation, ICNC 2007 (2007)
Stitt, G., Lysecky, R., Vahid, F.: Dynamic hardware/software partitioning: a first approach. In: Proceedings of Design Automation Conference (2003)
Jigang, W., Srikanthan, T., Jiao, T.: Algorithmic aspects for functional partitioning and scheduling in hardware/software co-design. Design Automation for Embedded Systems 12(4), 345–375 (2008)
Lopez-Vallejo, M., Lopez, J.C.: On the hardware-software partitioning problem: System modeling and partitioning techniques. ACM Trans. Des. Autom. Electron. Syst. 8(3), 269–297 (2003)
Vahid, F.: Partitioning sequential programs for CAD using a three-step approach. ACM Trans. Des. Autom. Electron. Syst. 7(3), 413–429 (2002)
Hong-lei, H.A.N., et al.: An Efficient Algorithm of Hardware/Software Partitioning and Scheduling on MPSoC. Computer Engineering and Science 33(9) (2011)
Wiangtong, T., Cheung, P.Y.K., Luk, W.: Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. Design Autom. for Emb. Sys. 6(4), 425–449 (2002)
Hong-xing, M.A., Xue-hai, Z., Yan-yan, G.A.O.: Algorithm for hardware/software task partitioning and scheduling on reconfigurable computing platform. Systems Engineering and Electronics 32(11) (2010)
Madsen, J., et al.: LYCOS: the Lyngby Co-Synthesis System. Design Automation for Embedded Systems 2(2), 195–235 (1997)
Dick, R.P., Rhodes, D.L., Wolf, W.: TGFF: task graphs for free. In: Proceedings of the Sixth International Workshop on Hardware/Software Codesign, CODES/CASHE 1998 (1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Li, C., Li, X., Wang, C., Zhou, X., Zeng, F. (2012). A Dependency Aware Task Partitioning and Scheduling Algorithm for Hardware-Software Codesign on MPSoCs. In: Xiang, Y., Stojmenovic, I., Apduhan, B.O., Wang, G., Nakano, K., Zomaya, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2012. Lecture Notes in Computer Science, vol 7439. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33078-0_24
Download citation
DOI: https://doi.org/10.1007/978-3-642-33078-0_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-33077-3
Online ISBN: 978-3-642-33078-0
eBook Packages: Computer ScienceComputer Science (R0)