Abstract
The latest commercial field programmable gate array (FPGA) like a Virtex-6 can perform partial reconfiguration (PR). PR can take full advantage of FPGA’s reconfigurability. However, PR bitstream (PRB) which created by authorized design flow cannot be relocated to other partially reconfigurable regions (PRRs). This indicates that the preparation of many PRBs are needed to perform a flexible partial reconfiguration. This paper presents a uniforming design technique for PRRs in order to relocate their PRB. Additionally, our design technique enables to implement large partial module by combining neighboring PRRs. To make relocatable, our technique only restricts the placement of reconfigurable resource and the route of interconnection. Therefore, our design can be achieved only using Xilinx EDA tools. Through verification, the correct operation of the relocated PRBs is confirmed.
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© 2012 Springer-Verlag Berlin Heidelberg
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Ichinomiya, Y., Amagasaki, M., Iida, M., Kuga, M., Sueyoshi, T. (2012). A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. In: Xiang, Y., Stojmenovic, I., Apduhan, B.O., Wang, G., Nakano, K., Zomaya, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2012. Lecture Notes in Computer Science, vol 7439. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33078-0_11
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DOI: https://doi.org/10.1007/978-3-642-33078-0_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-33077-3
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