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Exploring Object-Level Parallelism on Chip Multi-processors

  • Conference paper
Algorithms and Architectures for Parallel Processing (ICA3PP 2012)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 7440))

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Abstract

Object-oriented programming languages are prevalent at present and the inherent parallelism of a wide range of applications can be expressed as groups of concurrent objects. This paper proposes a new object-level parallel programming model to meet the challenge of parallel programming on chip multi-processors. This object-based computation model maps multiple software objects onto different physical processor cores at runtime. Independent objects can run concurrently and communicate with each other by synchronous, asynchronous, future and broadcast messages. In order to verify the efficiency of this model, a library implementation CPPLib of this model based on C++ is presented. The library implementation of this model requires no extension to existing object-oriented programming languages and provides good salability and portability. The performance of CPPLib is evaluated on both a dual-core desktop computer and an 8-core server using standard benchmarks. Experimental results show that CPPLib achieves average speedup levels of 1.5 and 3.6 on the dual-core desktop computer and the 8-core server, respectively, compared with their serial version.

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Author information

Authors and Affiliations

  1. Beijing Institute of Technology, Beijing, 100081, China

    Weixing Ji, Yizhuo Wang, Zhi Huang, Junqing Zhao & Xi Li

Authors
  1. Weixing Ji
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  2. Yizhuo Wang
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  3. Zhi Huang
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  4. Junqing Zhao
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  5. Xi Li
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Editor information

Editors and Affiliations

  1. School of Information Technology, Deakin University, Melbourne Burwood Campus, 221 Burwood Highway, 3125, Burwood, VIC, Australia

    Yang Xiang

  2. SEECS, University of Ottawa, 8, King Edward Ave, K1N 6N5, Ottawa, ON, Canada

    Ivan Stojmenovic

  3. Department of Intelligent Informatics, Kyushu Sangyo University, 2-3-1 Matsukadai, Higashi-ku, 813-8503, Fukuoka, Japan

    Bernady O. Apduhan

  4. School of Information Science and Engineering, Central South University, 410083, Changsha, Hunan Province, P.R. China

    Guojun Wang

  5. Department of Information Engineering, Hiroshima University, 1-4-1, Kagamiyama, 739-8527, Higashi-Hiroshima, Japan

    Koji Nakano

  6. School of Information Technologies, University of Sydney, Building J12, 2006, Sydney, NSW, Australia

    Albert Zomaya

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© 2012 Springer-Verlag Berlin Heidelberg

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Ji, W., Wang, Y., Huang, Z., Zhao, J., Li, X. (2012). Exploring Object-Level Parallelism on Chip Multi-processors. In: Xiang, Y., Stojmenovic, I., Apduhan, B.O., Wang, G., Nakano, K., Zomaya, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2012. Lecture Notes in Computer Science, vol 7440. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33065-0_9

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  • DOI: https://doi.org/10.1007/978-3-642-33065-0_9

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-33064-3

  • Online ISBN: 978-3-642-33065-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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