Multiplierless Design of Linear DSP Transforms

  • Levent Aksoy
  • Eduardo da Costa
  • Paulo Flores
  • José Monteiro
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 379)


The last two decades have seen tremendous effort on the development of high-level algorithms for the multiplierless design of constant multiplications, i.e., using only addition, subtraction, and shift operations. Among the different types of constant multiplications, the multiplication of a constant matrix by an input vector, i.e., the constant matrix-vector multiplication (CMVM) operation, is the most general case and occurs in many digital signal processing (DSP) systems. This chapter addresses the problem of minimizing the number of addition and subtraction operations in a CMVM operation and introduces a hybrid algorithm that incorporates efficient techniques. This chapter also describes how the hybrid algorithm can be modified to handle a delay constraint. The experimental results on a comprehensive set of instances show the efficiency of the hybrid algorithms at both high-level and gate-level, in comparison to previously proposed methods.


Constant matrix-vector multiplication common subexpression elimination difference method area and delay optimization 


  1. 1.
    Quereshi, F., Gustafsson, O.: Low-Complexity Reconfigurable Complex Constant Multiplication for FFTs. In: Proc. of IEEE International Symposium on Circuits and Systems, pp. 24–27 (2009)Google Scholar
  2. 2.
    Thong, J., Nicolici, N.: A Novel Optimal Single Constant Multiplication Algorithm. In: Proc. of Design Automation Conference, pp. 613–616 (2010)Google Scholar
  3. 3.
    Kang, H.J., Park, I.C.: FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing 48(8), 770–777 (2001)CrossRefGoogle Scholar
  4. 4.
    Hartley, R.: Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers. IEEE Trans. on Circuits and Systems II 43(10), 677–688 (1996)CrossRefGoogle Scholar
  5. 5.
    Boullis, N., Tisserand, A.: Some Optimizations of Hardware Multiplication by Constant Matrices. IEEE Trans. on Computers 54(10), 1271–1282 (2005)CrossRefGoogle Scholar
  6. 6.
    Wallace, C.: A Suggestion for a Fast Multiplier. IEEE Trans. on Electronic Computers 13(1), 14–17 (1964)zbMATHCrossRefGoogle Scholar
  7. 7.
    Gallagher, W., Swartzlander, E.: High Radix Booth Multipliers Using Reduced Area Adder Trees. In: Proc. of Asilomar Conference on Signals, Systems and Computers, pp. 545–549 (1994)Google Scholar
  8. 8.
    Nguyen, H., Chatterjee, A.: Number-Splitting With Shift-and-Add Decomposition for Power and Hardware Optimization in Linear DSP Synthesis. IEEE Trans. on VLSI 8(4), 419–424 (2000)CrossRefGoogle Scholar
  9. 9.
    Potkonjak, M., Srivastava, M., Chandrakasan, A.: Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination. IEEE Trans. on Computer-Aided Design of Integrated Circuits 15(2), 151–165 (1996)CrossRefGoogle Scholar
  10. 10.
    Aksoy, L., Costa, E., Flores, P., Monteiro, J.: Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. IEEE Trans. on Computer-Aided Design of Integrated Circuits 27(6), 1013–1026 (2008)CrossRefGoogle Scholar
  11. 11.
    Yurdakul, A., Dündar, G.: Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions. The Journal of VLSI Signal Processing 22(3), 163–172 (1999)CrossRefGoogle Scholar
  12. 12.
    Hosangadi, A., Fallah, F., Kastner, R.: Reducing Hardware Complexity of Linear DSP Systems by Iteratively Eliminating Two-Term Common Subexpressions. In: Proc. of Asia and South Pacific Design Automation Conference, pp. 523–528 (2005)Google Scholar
  13. 13.
    Aksoy, L., Costa, E., Flores, P., Monteiro, J.: Optimization Algorithms for the Multiplierless Realization of Linear Transforms. ACM Trans. on Design Automation of Electronic Systems 17(1), Article 3 (2012)Google Scholar
  14. 14.
    Bull, D., Horrocks, D.: Primitive Operator Digital Filters. IEE Proc. G: Circuits, Devices and Systems 138(3), 401–412 (1991)CrossRefGoogle Scholar
  15. 15.
    Dempster, A., Macleod, M.: Use of Minimum-Adder Multiplier Blocks in FIR Digital Filters. IEEE Trans. on Circuits and Systems II 42(9), 569–577 (1995)zbMATHCrossRefGoogle Scholar
  16. 16.
    Gustafsson, O., Wanhammar, L.: A Novel Approach to Multiple Constant Multiplication Using Minimum Spanning Trees. In: Proc. of IEEE Midwest Symposium on Circuits and Systems, pp. 652–655 (2002)Google Scholar
  17. 17.
    Voronenko, Y., Püschel, M.: Multiplierless Multiple Constant Multiplication. ACM Trans. on Algorithms 3(2) (2007)Google Scholar
  18. 18.
    Aksoy, L., Gunes, E., Flores, P.: Search Algorithms for the Multiple Constant Multiplications Problem: Exact and Approximate. Elsevier Journal on Microprocessors and Microsystems 34(5), 151–162 (2010)CrossRefGoogle Scholar
  19. 19.
    Dempster, A., Gustafsson, O., Coleman, J.: Towards an Algorithm for Matrix Multiplier Blocks. In: Proc. of IEEE European Conference on Circuit Theory and Design, pp. 1–4 (2003)Google Scholar
  20. 20.
    Gustafsson, O., Ohlsson, H., Wanhammar, L.: Low-Complexity Constant Coefficient Matrix Multiplication Using a Minimum Spanning Tree. In: Proc. of Nordic Signal Processing Symposium, pp. 141–144 (2004)Google Scholar
  21. 21.
    Avizienis, A.: Signed-digit Number Representation for Fast Parallel Arithmetic. IRE Trans. on Electronic Computers EC-10, 389–400 (1961)MathSciNetCrossRefGoogle Scholar
  22. 22.
    Garner, H.: Number Systems and Arithmetic. Advances in Computers 6, 131–194 (1965)zbMATHCrossRefGoogle Scholar
  23. 23.
    Reitwiesner, G.: Binary Arithmetic. Advances in Computers 1, 261–265 (1960)CrossRefGoogle Scholar
  24. 24.
    Cappello, P., Steiglitz, K.: Some Complexity Issues in Digital Signal Processing. IEEE Trans. on Acoustics, Speech, and Signal Processing 32(5), 1037–1041 (1984)zbMATHCrossRefGoogle Scholar
  25. 25.
    Ercegovac, M., Lang, T.: Digital Arithmetic. Morgan Kaufmann (2003)Google Scholar
  26. 26.
    Gustafsson, O.: Lower Bounds for Constant Multiplication Problems. IEEE Trans. on Circuits and Systems II 54(11), 974–978 (2007)CrossRefGoogle Scholar
  27. 27.
    Hosangadi, A., Fallah, F., Kastner, R.: Simultaneous Optimization of Delay and Number of Operations in Multiplierless Implementation of Linear Systems. In: Proc. of International Workshop on Logic Synthesis (2005)Google Scholar
  28. 28.
    Arfaee, A., Irturk, A., Laptev, N., Fallah, F., Kastner, R.: Xquasher: A Tool for Efficient Computation of Multiple Linear Expressions. In: Proc. of Design Automation Conference, pp. 254–257 (2009)Google Scholar
  29. 29.
    Lefevre, V.: Multiplication by an Integer Constant. Technical report, Institut National de Recherche en Informatique et en Automatique (2001)Google Scholar
  30. 30.
    Aksoy, L., Costa, E., Flores, P., Monteiro, J.: Finding the Optimal Tradeoff Between Area and Delay in Multiple Constant Multiplications. Elsevier Journal on Microprocessors and Microsystems 35(8), 729–741 (2011)CrossRefGoogle Scholar
  31. 31.
    Nangate website,

Copyright information

© IFIP International Federation for Information Processing 2012

Authors and Affiliations

  • Levent Aksoy
    • 1
  • Eduardo da Costa
    • 2
  • Paulo Flores
    • 3
  • José Monteiro
    • 3
  1. 1.INESC-IDLisbonPortugal
  2. 2.Universidade Católica de PelotasPelotasBrazil
  3. 3.INESC-ID/IST TU LisbonLisbonPortugal

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