High Performance SoC Design Using Magnetic Logic and Memory

  • Weisheng Zhao
  • Lionel Torres
  • Luís Vitório Cargnini
  • Raphael Martins Brum
  • Yue Zhang
  • Yoann Guillemenet
  • Gilles Sassatelli
  • Yahya Lakys
  • Jacques-Olivier Klein
  • Daniel Etiemble
  • Dafiné Ravelosona
  • Claude Chappert
Conference paper
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 379)


As the technolody node shrinks down to 90nm and below, high standby power becomes one of the major critical issues for CMOS highspeed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies, such as FRAM, MRAM, PCRAM and RRAM, are under investigation to bring the non-volatility into the logic circuits and then eliminate completely the standby power issue. Thanks to its infinite endurance, high switching/sensing speed and easy integration on top of CMOS process, MRAM is considered as the most promising one. Numerous logic circuits based on MRAM technology have been proposed and prototyped in the last years. In this paper, we present an overview and current status of these logic circuits and discuss their potential applications in the future from both physical and architectural points of view.


MRAM Non-volatile CPU Magnetic Logic Reconfigurable logic 


  1. 1.
    Weste, N., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective, 4th edn. Addison-Wesley Publishing Company, USA (2010)Google Scholar
  2. 2.
    Kang, S., Leblebici, Y.: CMOS digital integrated circuits: analysis and design. McGraw-Hill series in electrical engineering. McGraw-Hill (1999)Google Scholar
  3. 3.
    Kim, N., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J., Irwin, M., Kandemir, M., Narayanan, V.: Leakage current: Moore’s law meets static power. Computer 36(12), 68–75 (2003)CrossRefGoogle Scholar
  4. 4.
    Slaughter, J., Dave, R., Durlam, M., Kerszykowski, G., Smith, K., Nagel, K., Feil, B., Calder, J., DeHerrera, M., Garni, B., Tehrani, S.: High speed toggle mram with mgo-based tunnel junctions. In: IEEE International Electron Devices Meeting, IEDM Technical Digest, pp. 873–876 (December 2005)Google Scholar
  5. 5.
    Hoya, K., Takashima, D., Shiratake, S., Ogiwara, R., Miyakawa, T., Shiga, H., Doumae, S., Ohtsuki, S., Kumura, Y., Shuto, S., Ozaki, T., Yamakawa, K., Kunishima, I., Nitayama, A., Fujii, S.: A 64mb chain feram with quad-bl architecture and 200mb/s burst mode. In: IEEE International on Solid-State Circuits Conference, ISSCC 2006, Digest of Technical Papers, pp. 459–466 (February 2006)Google Scholar
  6. 6.
    Wong, H., Raoux, S., Kim, S., Liang, J., Reifenberg, J., Rajendran, B., Asheghi, M., Goodson, K.: Phase change memory. Proceedings of the IEEE 98(12), 2201–2227 (2010)CrossRefGoogle Scholar
  7. 7.
    Kund, M., Beitel, G., Pinnow, C.U., Rohr, T., Schumann, J., Symanczyk, R., Ufert, K.D., Muller, G.: Conductive bridging ram (cbram): an emerging non-volatile memory technology scalable to sub 20nm. In: IEEE International Electron Devices Meeting, IEDM Technical Digest, pp. 754–757 (December 2005)Google Scholar
  8. 8.
    Chappert, C., Fert, A., Van Dau, F.N.: The emergence of spin eletronics in data storage. Nature Materials 6(11), 813–823 (2007)CrossRefGoogle Scholar
  9. 9.
    Wolf, S.A., Awschalom, D.D., Buhrman, R.A., Daughton, J.M., Von Molnár, S., Roukes, M.L., Chtchelkanova, A.Y., Treger, D.M.: Spintronics: a spin-based electronics vision for the future. Science 294(5546), 1488–1495 (2001)CrossRefGoogle Scholar
  10. 10.
    Freescale: Freescale leads industry in commercializing mram technology; 4 mbit mram memory product now in volume production (July 2006),
  11. 11.
    Prejbeanu, I.L., Kerekes, M., Sousa, R.C., Sibuet, H., Redon, O., Dieny, B., Nozières, J.P.: Thermally assisted mram. Journal of Physics: Condensed Matter 19(16), 165218 (2007)Google Scholar
  12. 12.
    Sun, J.Z.: Spin angular momentum transfer in current-perpendicular nanomagnetic junctions. IBM Journal of Research and Development 50(1), 81–100 (2006)CrossRefGoogle Scholar
  13. 13.
    Kawahara, T., Takemura, R., Miura, K., Hayakawa, J., Ikeda, S., Lee, Y., Sasaki, R., Goto, Y., Ito, K., Meguro, I., Matsukura, F., Takahashi, H., Matsuoka, H., Ohno, H.: 2mb spin-transfer torque ram (spram) with bit-by-bit bidirectional current write and parallelizing-direction current read. In: IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, pp. 480–617 (February 2007)Google Scholar
  14. 14.
    Parkin, S.S.P., Hayashi, M., Thomas, L.: Magnetic domain-wall racetrack memory. Science 320(5873), 190–194 (2008)CrossRefGoogle Scholar
  15. 15.
    Lin, C., Kang, S., Wang, Y., Lee, K., Zhu, X., Chen, W., Li, X., Hsu, W., Kao, Y., Liu, M., Lin, Y., Nowak, M., Yu, N., Tran, L.: 45nm low power cmos logic compatible embedded stt mram utilizing a reverse-connection 1t/1mtj cell. In: 2009 IEEE International Electron Devices Meeting (IEDM), pp. 258–259 (December 2009)Google Scholar
  16. 16.
    Tsuchida, K., Inaba, T., Fujita, K., Ueda, Y., Shimizu, T., Asao, Y., Kajiyama, T., Iwayama, M., Sugiura, K., Ikegawa, S., Kishi, T., Kai, T., Amano, M., Shimomura, N., Yoda, H., Watanabe, Y.: A 64mb mram with clamped-reference and adequate-reference schemes. In: 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 258–259 (February 2010)Google Scholar
  17. 17.
    ITRS: International roadmap for semiconductors 2007 and 2008 update (2007),
  18. 18.
    Black, W.C., Das, B.: Programmable logic using giant-magnetoresistance and spin-dependent tunneling devices (invited). Journal of Applied Physics 87(9), 6674–6679 (2000)CrossRefGoogle Scholar
  19. 19.
    Zhao, W., Belhaire, E., Chappert, C., Mazoyer, P.: Spin transfer torque (stt)-mram–based runtime reconfiguration fpga circuit. ACM Trans. Embed. Comput. Syst. 9, 14:1–14:16 (2009)Google Scholar
  20. 20.
    Guillemenet, Y., Torres, L., Sassatelli, G., Bruchon, N., Hassoune, I.: A non-volatile run-time fpga using thermally assisted switching mrams. In: International Conference on Field Programmable Logic and Applications, FPL 2008, pp. 421–426 (September 2008)Google Scholar
  21. 21.
    Suzuki, D., Natsui, M., Ikeda, S., Hasegawa, H., Miura, K., Hayakawa, J., Endoh, T., Ohno, H., Hanyu, T.: Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array. In: 2009 Symposium on VLSI Circuits, pp. 80–81 (June 2009)Google Scholar
  22. 22.
    Yamamoto, S., Sugahara, S.: Nonvolatile delay flip-flop based on spin-transistor architecture and its power-gating applications. Japanese Journal of Applied Physics 49(9), 090204 (2010)Google Scholar
  23. 23.
    Sakimura, N., Sugibayashi, T., Nebashi, R., Kasai, N.: Nonvolatile magnetic flip-flop for standby-power-free socs. In: Custom Integrated Circuits Conference, CICC 2008, pp. 355–358. IEEE (September 2008)Google Scholar
  24. 24.
    Chaudhuri, S., Zhao, W., Klein, J.O., Chappert, C., Mazoyer, P.: Design of embedded mram macros for memory-in-logic applications. In: Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI, GLSVLSI 2010, pp. 155–158. ACM, New York (2010)CrossRefGoogle Scholar
  25. 25.
    Zhao, W., Belhaire, E., Dieny, B., Prenat, G., Chappert, C.: Tas-mram based non-volatile fpga logic circuit. In: International Conference on Field-Programmable Technology, ICFPT 2007, pp. 153–160 (December 2007)Google Scholar
  26. 26.
    Guillemenet, Y., Torres, L., Sassatelli, G.: Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories. Computers Digital Techniques, IET 4, 211–226 (2010)CrossRefGoogle Scholar
  27. 27.
    Devolder, T., Hayakawa, J., Ito, K., Takahashi, H., Ikeda, S., Crozat, P., Zerounian, N., Kim, J.V., Chappert, C., Ohno, H.: Single-shot time-resolved measurements of nanosecond-scale spin-transfer induced switching: Stochastic versus deterministic aspects. Phys. Rev. Lett. 100, 057206 (2008)Google Scholar
  28. 28.
    Ikeda, S., Miura, K., Yamamoto, H., Mizunuma, K., Gan, H.D., Endo, M., Kanai, S., Hayakawa, J., Matsukura, F., Ohno, H.: A perpendicular-anisotropy cofeb–mgo magnetic tunnel junction. Nature Materials 9(9), 721–724 (2010)CrossRefGoogle Scholar
  29. 29.
    Zhao, W., Chappert, C., Javerliac, V., Noziere, J.P.: High speed, high stability and low power sensing amplifier for mtj/cmos hybrid logic circuits. IEEE Transactions on Magnetics 45(10), 3784–3787 (2009)CrossRefGoogle Scholar
  30. 30.
    Faber, L.B., Zhao, W., Klein, J.O., Devolder, T., Chappert, C.: Dynamic compact model of spin-transfer torque based magnetic tunnel junction (mtj). In: 4th International Conference on Design Technology of Integrated Systems in Nanoscal Era, DTIS 2009, pp. 130–135 (April 2009)Google Scholar
  31. 31.
    Nepal, K., Bahar, R., Mundy, J., Patterson, W., Zaslavsky, A.: Designing mrf based error correcting circuits for memory elements. In: Proceedings of Design, Automation and Test in Europe, DATE 2006, vol. 1, pp. 1–2 (March 2006)Google Scholar
  32. 32.
    Dieny, B., Sousa, R.C., Herault, J., Papusoi, C., Prenat, G., Ebels, U., Houssameddine, D., Rodmacq, B., Auffret, S., Prejbeanu, L.D.B., et al.: Spin-transfer effect and its use in spintronic components. International Journal of Nanotechnology 7(4/5/6/7/8), 591 (2010)CrossRefGoogle Scholar
  33. 33.
    Zhao, W., Duval, J., Klein, J., Chappert, C.: A compact model for magnetic tunnel junction (mtj) switched by thermally assisted spin transfer torque (tas + stt). Nanoscale Research Letters 6(1), 368 (2011)CrossRefGoogle Scholar
  34. 34.
    Worledge, D.C., Hu, G., Abraham, D.W., Sun, J.Z., Trouilloud, P.L., Nowak, J., Brown, S., Gaidis, M.C., O’Sullivan, E.J., Robertazzi, R.P.: Spin torque switching of perpendicular ta|cofeb|mgo-based magnetic tunnel junctions. Applied Physics Letters 98(2), 22501 (2011)CrossRefGoogle Scholar
  35. 35.
    Sun, Z., Bi, X., Li, H., Wong, W., Ong, Z., Zhu, X., Wu, W.: Multi-retention level stt-ram cache designs with a dynamic refresh scheme. In: Proceedings of the 44th Annual ACM/IEEE International Symposium on Microarchitecture, MICRO 44, Porto Alegre, Brazil, pp. 329–338. IEEE Computer Society (December 2011)Google Scholar
  36. 36.
    Xilinx, I.: Spartan-3 fpga family data sheet (December 2009),
  37. 37.
    Torres, L., Guillemenet, Y., Ahmed, S.Z.: A dynamic reconfigurable mram based fpga. In: ERSA 2010 Keynote Paper, p. 10 (2010)Google Scholar
  38. 38.
    Zhao, W., Belhaire, E., Javerliac, V., Chappert, C., Dieny, B.: A non-volatile flip-flop in magnetic fpga chip. In: International Conference on Design and Test of Integrated Systems in Nanoscale Technology, DTIS 2006, pp. 323–326 (September 2006)Google Scholar
  39. 39.
    Kang, S.H.: Embedded stt-mram for mobile applications: Enabling advanced chip architectures. In: Non-Volatile Memories Workshop, San Diego, CA, USA (April 2010)Google Scholar
  40. 40.
    Kothari, L., Carter, N.P.: Architecture of a self-checkpointing microprocessor that incorporates nanomagnetic devices. IEEE Transactions on Computers 56(2), 161–173 (2007)MathSciNetCrossRefGoogle Scholar
  41. 41.
    Behin-Aein, B., Deepanjan Datta, S.S., Datt, S.: Proposal for an all-spin logic device with built-in memory. Nature Nanotechnology 5(4), 266–270 (2010)CrossRefGoogle Scholar
  42. 42.
    Allwood, D.A., Xiong, G., Faulkner, C.C., Atkinson, D., Petit, D., Cowburn, R.P.: Magnetic domain-wall logic. Science 309(5741), 1688–1692 (2005)CrossRefGoogle Scholar
  43. 43.
    Matsunaga, S., Hayakawa, J., Ikeda, S., Miura, K., Hasegawa, H., Endoh, T., Ohno, H., Hanyu, T.: Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions. Applied Physics Express 1(9), 091301 (2008)CrossRefGoogle Scholar
  44. 44.
    Sun, G., Dong, X., Xie, Y., Li, J., Chen, Y.: A novel architecture of the 3d stacked mram l2 cache for cmps. In: IEEE 15th International Symposium on High Performance Computer Architecture, HPCA 2009, pp. 239–249 (February 2009)Google Scholar
  45. 45.
    Lakys, Y., Zhao, W., Klein, J.O., Chappert, C.: Low power, high reliability magnetic flip-flop. Electronics Letters 46(22), 1493–1494 (2010)CrossRefGoogle Scholar
  46. 46.
    Burger, D., Austin, T.M.: The simplescalar tool set, version 2.0. SIGARCH Comput. Archit. News 25, 13–25 (1997)CrossRefGoogle Scholar
  47. 47.
    Lee, C., Potkonjak, M., Mangione-Smith, W.H.: Mediabench: a tool for evaluating and synthesizing multimedia and communicatons systems. In: Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, MICRO 30, pp. 330–335. IEEE Computer Society, Washington, DC (1997)Google Scholar
  48. 48.
    Gaisler, A.: Leon3 multiprocessing cpu core (February 2010),
  49. 49.
    Zhao, W., Torres, L., Cargnini, L.V., Brum, R.M., Zhang, Y., Guillemenet, Y., Sassatelli, G., Lakys, Y., Klein, J.-O., Etiemble, D., Ravelosona, D., Chappert, C.: High Performance SoC Design Using Magnetic Logic and Memory. In: Mir, S., et al. (eds.) VLSI-SoC 2011. IFIP AICT, vol. 379, pp. 10–33. Springer, Heidelberg (2012)Google Scholar
  50. 50.
    Mackay, K.: Tas, tas+stt-mram and magnetic logic unit, Property of Crocus Technology. Non authorized Publication (November 2011)Google Scholar
  51. 51.
    JC-42.3: Double data rate (ddr) sdram standard. Standard, JEDEC (2008),
  52. 52.
    Powell, M., Agarwal, A., Vijaykumar, T., Falsafi, B., Roy, K.: Reducing set-associative cache energy via way-prediction and selective direct-mapping. In: Proceedings of 34th ACM/IEEE International Symposium on Microarchitecture, MICRO-34, pp. 54–65 (2001)Google Scholar
  53. 53.
    Hennessy, J.L., Patterson, D.A.: Computer architecture: a quantitative approach, 4th edn., vol. 1. Elsevier - Morgan Kaufmann - Denise E. M. Penrose (2007)Google Scholar
  54. 54.
    Patterson, D.A., Hennessy, J.L.: Computer organization and design: the hardware/software interface (2005)Google Scholar
  55. 55.
    Boschma, B., Burns, D., Chin, R., Fiduccia, N., Hu, C., Reed, M., Rueth, T., Schumacher, F., Shen, V.: A 30 mips vlsi cpu. In: 36th IEEE International Solid-State Circuits Conference, ISSCC 1989, Digest of Technical Papers, pp. 82–83 (1989)Google Scholar
  56. 56.
    Nambu, H., Kanetani, K., Yamasaki, K., Higeta, K., Usami, M., Fujimura, Y., Ando, K., Kusunoki, T., Yamaguchi, K., Homma, N.: A 1.8-ns access, 550-mhz, 4.5-mb cmos sram. IEEE Journal of Solid-State Circuits 33(11), 1650–1658 (1998)CrossRefGoogle Scholar
  57. 57.
    Alvarez, J., Barkin, E., Chao, C.C., Johnson, B., D’Addeo, M., Lassandro, F., Nicoletta, G., Patel, P., Reed, P., Reid, D., Sanchez, H., Siegel, J., Snyder, M., Sullivan, S., Taylor, S., Vo, M.: 450 mhz powerpctm microprocessor with enhanced instruction set and copper interconnect. In: 1999 IEEE International Solid-State Circuits Conference, ISSCC 1999, Digest of Technical Papers, pp. 96–97 (1999)Google Scholar
  58. 58.
    Gharachorloo, K., Gupta, A., Hennessy, J.: Performance evaluation of memory consistency models for shared-memory multiprocessors. In: Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, United States. ASPLOS-IV, pp. 245–257. ACM, New York (1991),, doi:10.1145/106972.106997, ISBN: 0-89791-380-9
  59. 59.
    Gutierrez, A., Dreslinski, R., Wenisch, T., Mudge, T., Saidi, A., Emmons, C., Paver, N.: Full-system analysis and characterization of interactive smartphone applications. In: 2011 IEEE International Symposium on Workload Characterization (IISWC), pp. 81–90 (2011)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2012

Authors and Affiliations

  • Weisheng Zhao
    • 1
  • Lionel Torres
    • 3
  • Luís Vitório Cargnini
    • 3
  • Raphael Martins Brum
    • 3
  • Yue Zhang
    • 1
  • Yoann Guillemenet
    • 3
  • Gilles Sassatelli
    • 3
  • Yahya Lakys
    • 1
  • Jacques-Olivier Klein
    • 1
  • Daniel Etiemble
    • 2
  • Dafiné Ravelosona
    • 1
  • Claude Chappert
    • 1
  1. 1.IEF - Université Paris-Sud 11 / CNRSFrance
  2. 2.LRI - Université Paris-Sud 11 / CNRSFrance
  3. 3.LIRMM - Université Montpellier 2 / CNRSFrance

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