Adiabatic Technique for Designing Energy Efficient Logic Circuits

Abstract

Energy minimization is an important factor in designing digital circuits which are portable and battery operated.Irreversible logic operation causes the minimum dissipation of KT ln 2 joules of heat energy when each bit is erased.Reversible logic that employs adiabatic switching principles can be used to minimize dynamic power , which is the major contributor to total power dissipation. Reversible Energy Recovery Logic (RERL) belongs to fully adiabatic logic family and it eliminates non adiabatic energy loss by making use of reversible logic. RERL NAND/AND gate and RERL SR latch is proposed in this work using eight phase clocking scheme. This RERL circuits consume less energy compared with static CMOS logic circuits at low speed operation. The simulation result using HSPICE shows that RERL circuits consume less power compared with the static CMOS circuits.