Mapping Cores to Network-on-Chip in Digital Circuit Design by Using Tabu Search Approach

Abstract

The network-on-chip(NoC) is one of important aspects in digital circuit design, it attracted more and more attentions in electronic engineering. The NoC has been proposed as a promising solution to act as communication architecture because the number of cores in the systems-on-chip(SoC) is increased greatly. A lot of work needs to be carried out in the design of NoC, such as the determinations of the NoC communication backbone and communication protocols, the allocation of cores to various available nodes in NoC topology, that is the core mapping. The task of core mapping is to determine the topological placement of cores onto the nodes in NoC topology structure, and choose a path for each pair of IP cores. In this paper, the NoC structure with mesh topology is considered, a new approach is presented for the core mapping of network-on-chip by using Tabu search algorithm. The evolution operations in genetic algorithms are added to the Tabu search process to enhance the computation efficiency. The experimental results show that the time being needed to obtain the core mapping scheme by the approach proposed in this paper is lower than conventional genetic algorithm.