Abstract
The binary decision diagram is a graph representation of Boolean functions, it also can efficiently represent the logic functionality of digital circuits. The number of nodes in binary decision diagram depends on the variable ordering. A new method is presented in this paper for the variable ordering and the minimization of binary decision diagram, the method is based on adaptive hierarchy genetic algorithm, which uses two populations with hierarchy to evolve in parallel, and the operation parameters in the evolution procedure are adjusted dynamically as the changes of environment. The individual representation scheme corresponding to binary decision diagram, and the implementation steps of adaptive hierarchy genetic algorithm, are given in detail. Besides, the application of the method for the test generation of digital circuits is given. A lot of experimental results show that the binary decision diagrams with smaller number of nodes can be obtained by the method proposed in this paper, and the test vectors of faults in digital circuits can also be produced.
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Pan, Z., Chen, L. (2013). Minimization of Binary Decision Diagrams by Adaptive Hierarchy Genetic Algorithm and Its Application in Circuit Test Generation. In: Jin, D., Lin, S. (eds) Advances in Mechanical and Electronic Engineering. Lecture Notes in Electrical Engineering, vol 178. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31528-2_29
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DOI: https://doi.org/10.1007/978-3-642-31528-2_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31527-5
Online ISBN: 978-3-642-31528-2
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