Abstract
Modern multicore processor technology can fairly easily deliver special accelerator processors dedicated to fast optimised execution of critical computational functions. Multi CMP (Chip Multi-Processor) systems can be composed as a set of dedicated and general purpose computational modules interconnected by a global data exchange network. The paper proposes special program scheduling algorithms for such systems. Dedicated CMP modules assumed in the paper are based on a new data communication model called communication on the fly. It enables strong reduction of inter–process and inter–core communication overheads for intensively shared data.
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References
Nurmi, J., Tenhunen, H., Isoaho, J., Jantsch, A. (eds.): Interconnect–Centric Design for Advanced SOC and NOC. Springer (2004)
Kundu, S., Peh, L.S.: On–Chip Interconnects for Multicores. IEEE Micro, 3–5 (September-October 2007)
Owens, J.D., et al.: Research Challenges for On–Chip Interconnection Networks. IEEE Micro, 96–108 (September-October 2007)
Milenkovic, A., Milutinovic, V.: Cache Injection: A Novel Technique for Tolerating Memory Latency in Bus-Based SMPs. In: Bode, A., Ludwig, T., Karl, W.C., Wismüller, R. (eds.) Euro-Par 2000. LNCS, vol. 1900, pp. 558–566. Springer, Heidelberg (2000)
Tudruj, M., Maśko, Ł.: Dynamic SMP Clusters with Communication on the Fly in NoC Technology for Very Fine Grain Computations. In: 3rd Int. Symp. on Parallel and Distributed Computing, ISPDC 2004, Cork, pp. 97–104 (July 2004)
Tudruj, M., Maśko, Ł.: Towards Massively Parallel Computations Based on Dynamic SMP Clusters wih Communication on the Fly. In: Proceedings of the 4th International Symposium on Parallel and Distributed Computing, ISPDC 2005, Lille, France, July 4-6, pp. 155–162. IEEE CS Press (2005)
Tudruj, M., Maśko, Ł.: Data Transfers on the Fly for Hierarchical Systems of Chip Multi–Processors. In: Wyrzykowski, R., et al. (eds.) PPAM 2011, Part I. LNCS, vol. 7203, pp. 50–59. Springer, Heidelberg (2012)
Masko, Ł., Dutot, P.–F., Mounié, G., Trystram, D., Tudruj, M.: Scheduling Moldable Tasks for Dynamic SMP Clusters in SoC Technology. In: Wyrzykowski, R., Dongarra, J., Meyer, N., Waśniewski, J. (eds.) PPAM 2005. LNCS, vol. 3911, pp. 879–887. Springer, Heidelberg (2006)
Maśko, Ł., Tudruj, M.: Task Scheduling for SoC–Based Dynamic SMP Clusters with Communication on the Fly. In: 7th Int. Symp. on Parallel and Distributed Computing, ISPDC 2008, pp. 99–106 (2008)
Hwang, J.-J., Chow, Y.-C., Anger, F.D., Lee, C.-Y.: Scheduling precedence graphs in systems with interprocessor communication times. SIAM Journal on Computing 18(2) (1989)
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Tudruj, M., Maśko, Ł. (2012). Scheduling Parallel Programs Based on Architecture–Supported Regions. In: Wyrzykowski, R., Dongarra, J., Karczewski, K., Waśniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2011. Lecture Notes in Computer Science, vol 7204. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31500-8_6
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DOI: https://doi.org/10.1007/978-3-642-31500-8_6
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31499-5
Online ISBN: 978-3-642-31500-8
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