Abstract
In the embedded system design Through-silicon-via (TSV) based 3D stacked ICs (SICs) play an important role in semiconductor industry. But testing of these SICs are required during 3D assembly because different die stacking steps may introduce defects. In this paper, we address test architecture optimization for 3D stacked ICs implemented with hard die means where die-level test architecture is fixed. We consider two different SIC configurations and derive optimal solution to minimize overall test time when complete stack and multiple partial stacks, need to be tested. Results are performed for two handcrafted 3D SICs comprising of various SoCs from ITC’02 SoC test benchmarks. In this work we consider the test architecture optimization for 3D SIC where each die consists of one SoC. We present test schedules and corresponding test lengths for every multiple insertions and also show that total test lengths are decreased with the increasing number of test pins.
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Roy, S.K., Roy, D., Giri, C., Rahaman, H. (2012). Post-bond Stack Testing for 3D Stacked IC. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_8
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DOI: https://doi.org/10.1007/978-3-642-31494-0_8
Publisher Name: Springer, Berlin, Heidelberg
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