Abstract
We present a technique to reduce the power of combinational circuits during testing. Power dissipation of IC during test mode is greater than the IC’s normal mode of functioning. During testing a significant fraction of test power is dissipated in the combinational circuits. To reduce the test power we proposed a modified structure of scan flip-flop in our previous work. In this paper we present the two possible gating techniques for the modified scan flip-flop to reduce the power dissipation due to unnecessary switching of combinational circuits too. The proposed method is implemented in some of the ISCAS benchmark circuits to observe the percentage of power saving after applying the gating technique. The result of our experiment shows that, about 13%-18.5% more power saving in addition to the proposed scan flip-flop.
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Jayagowri, R., Gurumurthy, K.S. (2012). Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_7
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DOI: https://doi.org/10.1007/978-3-642-31494-0_7
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