Abstract
In this paper a circuit design technique to reduce dynamic power consumption of a new CMOS domino logic family called feedthrogh logic (FTL)is presented. The proposed modified circuit has very low dynamic power consumption compared to recently proposed circuit techniques for FTL logic styles. The proposed circuit is simulated using 0.18 μm, 1.8 V CMOS process technology. We compare an 8-bit ripple carry adder and a D-latch designed by both FTL and proposed FTL structure in terms of power consumption, average propagation delay and clock rate.
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© 2012 Springer-Verlag Berlin Heidelberg
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Sahoo, S.R., Mahapatra, K.K. (2012). Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_46
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DOI: https://doi.org/10.1007/978-3-642-31494-0_46
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
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