Abstract
Network-on-Chip (NoC) based Built-In-Self Test (BIST) architecture is an acceptable solution for testing embedded memory cores in Systems-On-Chip. The reuse of the available on-chip network to act as Test Access Mechnism brings down the area overhead as well as reduces test power. However, reducing the time to test still remains a problem due to latency in transporting the test instruction from BIST circuit to the memory cores. We have proposed a NoC based test architecture where a number of BIST controllers are shared by memory cores. A Particle Swarm Optimization (PSO) based technique is used (i) to place the BIST controllers at fixed locations and (ii) to form clusters of memories sharing the BIST controllers. This reduces the test instruction transport latency which in turn reduces the total test time of memory cores. Experimental results on different sizes of mesh based NoC confirm the effectiveness of our PSO based approach over heuristic techniques reported in literature as well as used in the industry.
Keywords
- Particle Swarm Optimization
- Area Overhead
- Memory Core
- Uncapacitated Facility Location Problem
- Test Architecture
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Ghoshal, B., Kundu, S., Sengupta, I., Chattopadhyay, S. (2012). Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_39
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DOI: https://doi.org/10.1007/978-3-642-31494-0_39
Publisher Name: Springer, Berlin, Heidelberg
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