Abstract
This paper presents an efficient FPGA based architecture for Sobel edge detection algorithm in respect of both time and space complexity. Various edge detection algorithms are typically used in image processing, artificial intelligence etc. In this paper the Sobel edge detection algorithm using hardware description language and its implementation in Field Programmable Gate Array (FPGA) device is presented in an efficient way. Sobel edge detection algorithm is chosen due to its property of less deterioration in high levels of noise. The result shows a significant improvement of time and space complexity over an existing architecture.
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© 2012 Springer-Verlag Berlin Heidelberg
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Halder, S., Bhattacharjee, D., Nasipuri, M., Basu, D.K. (2012). A Fast FPGA Based Architecture for Sobel Edge Detection. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_34
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DOI: https://doi.org/10.1007/978-3-642-31494-0_34
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
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