Abstract
This paper presents a 4 × 20 Gb/s 29-1 pseudo-random binary sequence (PRBS) generator in 90nm CMOS technology to test a 4-bit 20 GS/s digital to analog converter (DAC). The architecture results in generation of four de-correlated sequences from a single 9-bit LFSR (linear feedback shift register) with minimal circuitry. Improved CML (current mode logic) multiplexer design ensures peak-to-peak jitter of 1.7 psec, and negligible amplitude variation. The data latches are clocked at half-rate in order to reduce power dissipation, and are followed by 2:1 multiplexers to achieve the desired data-rate, consuming 51mW per output lane (total 204 mW) of power from a 1 V supply. The PRBS and DAC can together be used for generating pseudo-random multi-level test symbol sequences for high-speed communication links.
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Sakare, M., Singh, M., Gupta, S. (2012). A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_29
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DOI: https://doi.org/10.1007/978-3-642-31494-0_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
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