Reusable and Scalable Verification Environment for Memory Controllers

Abstract

With the increase in design complexity, verification times are growing significantly. Reuse of verification environment is an important means of reducing the verification effort. This paper address the problem of developing a reusable and a scalable verification environment for memory controllers. Though the architecture of different memory controllers varies significantly, they share a common transactional property. This property is exploited to develop a reusable verification environment. The proposed transactional verification environment coupled with the assertion based latency checkers achieve near cycle-accurate efficiency. The proposed verification environment is also scalable to verify memory controllers with multiple ports. We applied the above approach for the verification of three memory controllers, and results showed significant improvement in productivity and effectiveness.