Abstract
This paper presents the different design schemes of the phase frequency detector (PFD) and compares with the output simulation results. The circuits that have been considered are the tristate linear D-FF type PFD, conventional Phase frequency Detector (conPFD), precharge type phase frequency detector (ptPFD), ncPFD in zero degree phase offset version, modified ncPFD with π rad phase offset, and TSPC-PFD. Although, PFDs are suffered from non ideal effects, therefore, to eliminate these effects a proposed PFD has been designed. The simulation results are focused on exploring the jitter, power dissipation, phase noise, and output noise of the different PFDs. The different PFD circuits are designed using 0.18μm CMOS process technology with 1.8 V supply voltage.
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© 2012 Springer-Verlag Berlin Heidelberg
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Hati, M.K., Bhattacharyya, T.K. (2012). A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_19
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DOI: https://doi.org/10.1007/978-3-642-31494-0_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
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