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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 175))

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Abstract

Digital logic circuits cover a big part of semiconductor device production. Depending on their applications, digital logic integrated circuits (ICs) are divided into two main branches: high-performance (e.g. for microprocessor applications) and low-power (e.g. for mobile applications) [1]. The main requirements are lower power consumption, higher performance, and higher device density per chip. Before discussing the strategies to achieve these goals, the main components contributing the power dissipation in a CMOS circuit are briefly described.

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References

  1. The International Technology Roadmap for Semiconductors (ITRS) (2009)

    Google Scholar 

  2. Veendrick, H.: Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits. IEEE J. Solid-State Circuits SC-19(4), 468–473 (1984)

    Article  Google Scholar 

  3. Roy, K., Mukhopahyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(3), 305–327 (2003)

    Article  Google Scholar 

  4. Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices. Cambridge Univ. Press, New York (1998)

    Google Scholar 

  5. Chang, L., Tang, S., King, T.-J., Bokor, J., Hu, C.: Gate-length scaling and threshold voltage control of double-gate MOSFETs. In: IEDM Tech. Dig., pp. 719–722 (2000)

    Google Scholar 

  6. Pethe, A., Krishnamohan, T., Kim, D., Oh, S., Wong, H.-S.P., Nishi, Y., Saraswat, K.C.: Investigation of the performance limits of III-V double-gate n-MOSFETs. In: IEDM Tech. Dig., pp. 605–608 (2005)

    Google Scholar 

  7. Yau, L.D.: A simple theory to predict the threshold voltage of short-channel IGFET’s. Solid-State Electronics 17(10), 1059–1063 (1974)

    Article  Google Scholar 

  8. Taur, Y., Wind, S., Mii, Y., Lii, Y., Moy, D., Jenkins, K., Chen, C.L., Coane, P.J., Klaus, D., Bucchignano, J., Rosenfield, M., Thomson, M., Polcari, M.: High performance 0.1 μm CMOS devices with 1.5 V power supply. In: IEDM Tech. Dig., pp. 127–130 (1993)

    Google Scholar 

  9. Joodaki, M.: On the extraction of the external drain and source resistors and effective channel length in Si-MOSFET. Submitted to Solid-State Electronics

    Google Scholar 

  10. Chen, J., Chan, T.Y., Chen, I.C., Ko, P.K., Hu, C.: Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Letters 8(11), 515–517 (1987)

    Article  Google Scholar 

  11. Bohr, M.: The new era of scaling in an SoC world. In: IEEE Int. Solid-State Circuits Conf., pp. 23–28 (2009)

    Google Scholar 

  12. Dennard, R., Gaensslen, F.H., Yu, H.-N., Rideout, V.L., Bassous, E., Leblanc, A.R.: Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circuits 9(5), 256–268 (1974)

    Article  Google Scholar 

  13. Philip Wong, H.-S., Frank, D.J., Solomon, P.M., Wann, C.H.J., Welser, J.J.: Nanoscale CMOS. Proc. IEEE 87(4), 537–570 (1999)

    Article  Google Scholar 

  14. Davari, B., Dennard, R.H., Shahidi, G.G.: CMOS scaling, the next ten years. Proc. IEEE 83(4), 595–606 (1995)

    Article  Google Scholar 

  15. Nowak, E.J.: Ultimate CMOS ULSI Performance. In: IEDM Tech. Dig., pp. 115–118 (1993)

    Google Scholar 

  16. Lo, S.-H., Buchanan, D.A., Taur, Y., Wang, W.: Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s. IEEE Electron Device Letters 18(5), 209–211 (1997)

    Article  Google Scholar 

  17. Lee, B.H., Oh, J., Tseng, H.H., Jammy, R., Huff, H.: Gate stack technology for nanoscale devices. Materialstoday 9(6), 32–40 (2006)

    Google Scholar 

  18. Gusev, E.P., Narayanan, V., Frank, M.M.: Advanced high-k dielectric stacks with polySi and metal gates: Recent progress and current challenges. IBM J. Res. & Dev. 50(4/5), 387–410 (2006)

    Article  Google Scholar 

  19. Hoeneisen, B., Mead, C.A.: Fundamental limitations in microelectronics-I. MOS technology. Solid-State Electron. 15(7), 819–829 (1972)

    Article  Google Scholar 

  20. Wong, H.S., Taur, Y.: Three-dimensional atomistic simulation of discrete random dopant distribution effects in sub-0.1 μm MOSFET’s. In: IEDM Tech. Dig., pp. 705–708 (1993)

    Google Scholar 

  21. Uchino, T., Shiba, T., Ohnishi, K., Miyauchit, A., Nakatat, M., Inouet, Y., Suzukit, T.: A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-μm CMOS ULSIs. In: IEDM Tech. Dig., pp. 479–482 (1997)

    Google Scholar 

  22. Tucker, J.R., Wang, C., Carney, P.S.: Silicon field‐effect transistor based on quantum tunneling. Applied Physics Letters 65(5), 618–620 (1994)

    Article  Google Scholar 

  23. Ghani, T., Armstrong, M., Auth, C., Bost, M., Charvat, P., Glass, G., Hoffiann, T., Johnson, K., Kenyon, C., Klaus, J., Mclntyre, B., Mistry, K., Murthy, A., Sandford, J., Silberstein, M., Sivakumar, S., Smith, P., Zawadzki, K., Thompson, S., Bohr, M.: A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. In: IEDM Tech. Dig., pp. 978–980 (2003)

    Google Scholar 

  24. Thompson, S., Armstrong, M., Auth, C., Alavi, M., Buehler, M., Chau, R., Cea, S., Ghani, T., Glass, G., Hoffman, T., Jan, C.-H., Kenyon, C., Klaus, J., Kuhn, K., Ma, Z., Mcintyre, B., Mistry, K., Murthy, A., Obradovic, B., Nagisetty, R., Nguyen, P., Sivakumar, S., Shaheed, R., Shifren, L., Tufts, B., Tyagi, S., Bohr, M., El-Mansy, Y.: A 90nm logic technology featuring strained-silicon. IEEE Trans. Electron Devices 51(11), 1790–1797 (2004)

    Article  Google Scholar 

  25. Kimura, S., Hisamoto, D., Sugii, N.: Prospect of Si semiconductor devices in nanometer era. Hitachi Review 54(1), 2–8 (2005)

    Google Scholar 

  26. Mistry, K., Allen, C., Auth, C., Beattie, B., Bergstrom, D., Bost, M., Brazier, M., Buehler, M., Cappellani, A., Chau, R., Choi, C.-H., Ding, G., Fischer, K., Ghani, T., Grover, R., Han, W., Hanken, D., Hattendorf, M., He, J., Hicks, J., Huessner, R., Ingerly, D., Jain, P., James, R., Jong, L., Joshi, S., Kenyon, C., Kuhn, K., Lee, K., Liu, H., Maiz, J., McIntyre, B., Moon, P., Neirynck, J., Pae, S., Parker, C., Parsons, D., Prasad, C., Pipes, L., Prince, M., Ranade, P., Reynolds, T., Sandford, J., Shifren, L., Sebastian, J., Seiple, J., Simon, D., Sivakumar, S., Smith, P., Thomas, C., Troeger, T., Vandervoorn, P., Williams, S., Zawadzki, K.: A 45nm logic technology with high-κ + metal-gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. In: IEDM Tech. Dig., pp. 247–250 (December 2007)

    Google Scholar 

  27. Auth, C., Cappellani, A., Chun, J.-S., Dalis, A., Davis, A., Ghani, T., Glass, G., Glassman, T., Harper, M., Hattendorf, M., Hentges, P., Jaloviar, S., Joshi, S., Klaus, J., Kuhn, K., Lavric, D., Lu, M., Mariappan, H., Mistry, K., Norris, B., Rahhal-orabi, N., Ranade, P., Sandford, J., Shifren, L., Souw, V., Tone, K., Tambwe, F., Thompson, A., Towner, D., Troeger, T., Vandervoorn, P., Wallace, C., Wiedemer, J., Wiegand, C.: 45nm high-κ + metal gate strain-enhanced transistors. In: Symp. VLSI Technology, pp. 128–129 (June 2008)

    Google Scholar 

  28. Wann, C.H., Noda, K., Tanaka, T., Yoshida, M., Hu, C.: A comparative study of advanced MOSFET concepts. IEEE Trans. Electron Devices 43, 1742–1753 (1996)

    Article  Google Scholar 

  29. Wong, H.-S.P.: Beyond the conventional transistor. IBM J. Res. Develop. 46(2-3), 133–168 (2002)

    Article  Google Scholar 

  30. Choi, Y.-K., Asano, K., Lindert, N., Subramanian, V., King, T.-J., Bokor, J., Hu, C.: Ultrathin-body SOI MOSFET for deep-sub-tenth micron era. IEEE Electron Device Lett. 21(5), 254–255 (2000)

    Article  Google Scholar 

  31. Banna, S.R., Chan, P.C.H., Chan, M., Fung, S.K.H., Ko, P.K.: Fully depleted CMOS/SOI device design guidelines for low-power applications. IEEE Trans. Electron Devices 46(4), 754–761 (1999)

    Article  Google Scholar 

  32. Doris, B., Ieong, M., Zhu, H., Zhang, Y., Steen, M., Natzle, W., Callegari, S., Narayanan, V., Cai, J., Ku, S.H., Jamison, P., Li, Y., Ren, Z., Ku, V., Boyd, D., Kanarsky, T., D’Emic, C., Newport, M., Dobuzinsky, D., Deshpande, S., Pehus, J., Jammy, R., Haensch, W.: Device design considerations for ultra-thin SOI MOSFETs. In: IEDM Tech. Dig., pp. 631–634 (2002)

    Google Scholar 

  33. Sekigawa, T., Hayashi, Y.: Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate. Solid State Electronics 27(8-9), 827–828 (1984)

    Article  Google Scholar 

  34. Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J., Elewa, T.: Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Lett. 8(9), 410–412 (1987)

    Article  Google Scholar 

  35. Frank, D.J., Laux, S.E., Fischetti, M.V.: Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? In: IEDM Tech. Dig., pp. 553–556 (1992)

    Google Scholar 

  36. Wong, H.-S.P., Frank, D.J., Solomon, P.M., Wann, C.H.J., Welser, J.J.: Nanoscale CMOS. Proc. IEEE 87(4), 537–570 (1999)

    Article  Google Scholar 

  37. Solomon, P.M., Guarini, K.W., Zhang, Y., Chan, K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O., Hovel, H.J., Bucchignano, J.J., Cabral Jr., C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K., Yoon, J.H., Babich, I.V., Treichler, J., Kozlowski, P.M., Newbury, J.S., D’Emic, C.P., Sicina, R.M., Benedict, J., Wong, H.S.P.: Two gates are better than one [double-gate MOSFET process]. IEEE Circuits and Devices Magazine 19(1), 48–62 (2003)

    Article  Google Scholar 

  38. Huang, X., Lee, W.-C., Kuo, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y.-K., Asano, K., Subramanian, V., King, T.-J., Bokor, J., Hu, C.: Sub-50 nm FinFET: PMOS. In: IEDM Tech. Dig., pp. 67–70 (1999)

    Google Scholar 

  39. Yu, B., Chang, L., Ahmed, S., Wang, H., Bell, S., Yang, C.-Y., Tabery, C., Ho, C., Xiang, Q., King, T.-J., Bokor, J., Hu, C., Lin, M.-R., Kyser, D.: FinFET scaling to 10 nm gate length. In: IEDM Tech. Dig., pp. 251–254 (2002)

    Google Scholar 

  40. Doyle, B., Boyanov, B., Datta, S., Doczy, M., Hareland, S., Jin, B., Kavalieros, J., Linton, T., Rios, R., Chau, R.: Tri-gate fully-depleted CMOS transistors: fabrication, design and layout. In: Symp. VLSI Tech., pp. 133–134 (2003)

    Google Scholar 

  41. Su, L.T., Jacobs, J.B., Chung, J.E., Antoniadis, D.A.: Short-channel effects in deep-submicrometer SOI MOSFETS. In: Proc. IEEE Int. SOI Conf., pp. 112–113 (1993)

    Google Scholar 

  42. Wong, H.-S.P., Chan, K., Taur, Y.: Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel. In: IEDM Tech. Dig., pp. 427–430 (1997)

    Google Scholar 

  43. Hisamoto, D., Kaga, T., Takeda, E.: Impact of the vertical SO1 ‘DELTA’ structure on planar device technology. IEEE Trans. Electron Devices 38(6), 1419–1424 (1991)

    Article  Google Scholar 

  44. Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., Hu, C.: FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)

    Article  Google Scholar 

  45. Colinge, Gao, M., Romano-Rodriguez, A., Maes, H., Claeys, C.: Silicon-on-insulator gate-all-around device. In: IEDM Tech. Dig., pp. 595–598 (1990)

    Google Scholar 

  46. Colinge, J.P.: Multiple-gate SOI MOSFETs. Solid-State Electronics 48(6), 897–905 (2004)

    Article  Google Scholar 

  47. Skotnicki, T., Hutchby, J.A., King, T.-J., Wong, H.-S.P., Boeuf, F.: The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits and Devices Magazine 21(1), 16–26 (2005)

    Article  Google Scholar 

  48. Risch, L.: Pushing CMOS beyond the roadmap. Solid-State Electronics 50(4), 527–535 (2005)

    Article  Google Scholar 

  49. Balestra, F.: SOI nanodevices and materials for CMOS ULSI. Journal of Telecommunications and Information Technology, 3–13 (2007)

    Google Scholar 

  50. Saint-Martin, J., Bournel, A., Dollfus, P.: Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation. Solid-State Electronics 50(1), 94–101 (2006)

    Article  Google Scholar 

  51. Widiez, J., Daud, F., Vinet, M., Poiroux, T., Previtalil, B., Mouis, M., Deleonibus, S.: Experimental gate misalignment analysis on double gate SO1 MOSFETs. In: Proc. IEEE Int. SOI Conf., pp. 185–186 (2004)

    Google Scholar 

  52. Bansal, A., Paul, B.C., Roy, K.: Impact of gate underlap on gate capacitance and gate tunneling current in 16nm DGMOS devices. In: Proc. IEEE Int. SOI Conf., pp. 94–95 (2004)

    Google Scholar 

  53. Chang, L., Choi, Y.-K., Ha, D., Ranade, P., Xiong, S., Bokor, J., Hu, C., King, T.-J.: Extremely Scaled Silicon Nano-CMOS Devices. Proceedings of the IEEE 91(11), 1860–1873 (2003)

    Article  Google Scholar 

  54. Sato, T., Takeishi, Y., Hara, H.: Mobility anisotropy of electrons in inversion layers on oxidized silicon surfaces. Phy. Rev. B 4, 1950–1960 (1971)

    Article  Google Scholar 

  55. Chau, R., Doyle, B., Kavalieros, J., Barlage, D., Murthy, A., Doczy, M., Arghavani, R., Datta, S.: Advanced depleted-substrate transistor: single-gate, double-gate and tri-gate. In: Proc. Solid State Devices and Materials, pp. 68–69 (2002)

    Google Scholar 

  56. Wu, W., Chan, M.: Analysis of geometry-dependent parasitic in multifin double-gate FinFETs. IEEE Trans. Electron Devices 54(4), 692–698 (2007)

    Article  Google Scholar 

  57. Giacominia, R., Martino, J.A.: Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects. Journal of The Electrochemical Society 155(4), H213–H217 (2008)

    Google Scholar 

  58. Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J., Elewa, T.: Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Letters 8(9), 410–412 (1987)

    Article  Google Scholar 

  59. Omura, Y., Horiguchi, S., Tabe, M., Kishi, K.: Quantum-mechanical effects on the threshold voltage of ultrathin SOI nMOSFETs. IEEE Electron Device Letters 14(12), 569–571 (1993)

    Article  Google Scholar 

  60. Kim, D., Krishnamohan, T., Nishi, Y., Saraswat, K.C.: Band to band tunneling limited off state current in ultra-thin body double gate FETs with high mobility materials: III-V, Ge and strained Si/Ge. In: Int. Conf. Simulation of Semiconductor Processes and Devices, pp. 389–392 (2006)

    Google Scholar 

  61. Colinge, J.P.: Multi-gate SOI MOSFETs. Microelectronic Engineering 84(9-10), 2071–2076 (2007)

    Article  Google Scholar 

  62. Hisamoto, D., Sugii, N., Torii, K., Shima, A., Ryuzaki, D.: ULSI devices: current status and future prospects of research and development. Hitachi Review 56(3), 25–33 (2007)

    Google Scholar 

  63. Shima, A., Wang, Y., Talwar, S., Hiraiwa, A.: Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS. In: Symp. VLSl Tech., pp. 174–175 (2004)

    Google Scholar 

  64. Ito, T., Iinuma, T., Murakoshi, A., Akutsu, H., Arikado, T., Okumura, T., Yoshioka, M., Owada, T., Imaoka, Y., Murayama, H., Kusuda, T.: Flash lamp anneal technology for effectively activating ion implanted Si. In: Int. Conf. Solid State Devices and Materials (SSDM), pp. 182–183 (2001)

    Google Scholar 

  65. Xie, Y.H., Monroe, D., Fitzgerald, E.A., Silverman, P.J., Thiel, F.A., Watson, G.P.: Very high mobility two-dimensional hole gas in Si/GexSi1 − x/Ge structures grown by molecular beam epitaxy. Appl. Phys. Lett. 63(16), 2263–2264 (1993)

    Article  Google Scholar 

  66. Konig, U., Schaffler, F.: p-type Ge-channel MODFET’s with high transconductance grown on Si substrates. IEEE Electron Device Lett. 14(4), 205–207 (1993)

    Article  Google Scholar 

  67. Chau, R., Datta, S., Majumdar, A.: Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications. In: IEEE Symp. Compound Semiconductor Integrated Circuit, pp. 17–20 (2005)

    Google Scholar 

  68. Lauhon, L.J., Gudiksen, M.S., Wang, D., Lieber, C.M.: Epitaxial core-shell and core-multishell nanowire heterostructures. Nature 420(6911), 57–61 (2002)

    Article  Google Scholar 

  69. Cui, Y., Zhong, Z., Wang, D., Wang, W.U., Lieber, C.M.: High performance silicon nanowire field effect transistors. Nano Lett. 3(2), 149–152 (2003)

    Article  Google Scholar 

  70. Cui, Y., Duan, X., Hu, J., Lieber, C.M.: Doping and electrical transport in silicon nanowires. J. Phys. Chem. B 104(22), 5213–5216 (2000)

    Article  Google Scholar 

  71. Tans, S.J., Verschueren, A.R.M., Dekker, C.: Room-temperature transistor based on a single carbon nanotube. Nature 393(6681), 49–52 (1998)

    Google Scholar 

  72. Durkop, T., Getty, S.A., Cobas, E., Fuhrer, M.S.: Extraordinary mobility in semiconducting carbon nanotubes. Nano Lett. 4(1), 35–39 (2004)

    Article  Google Scholar 

  73. Obradovic, B., Kotlyar, R., Heinz, F., Matagne, P., Rakshit, T., Giles, M.D., Stettler, M.A., Nikonov, D.E.: Analysis of graphene nanoribbons as a channel material for field-effect transistors. Appl. Phys. Lett. 88(14), 142102 (2006)

    Article  Google Scholar 

  74. Novoselov, K.: Graphene: mind the gap. Nature Materials 6(10), 720–721 (2007)

    Article  Google Scholar 

  75. Joodaki, M.: An extended drain current conductance extraction method and its application to DRAM support and array devices. Solid-State Electronics 53(9), 1020–1031 (2009)

    Article  Google Scholar 

  76. Heineck, L., Graf, W., Popp, M., Savignac, D., Moll, H.-P., Tews, R., Temmler, D., Kar, G., Schmid, J., Rouhanian, M., Uhlig, I., Goldbach, M., Landgraf, E., Dreeskornfeld, L., Drubba, M., Lukas, S., Weinmann, D., Roesner, W., Mueller, W.: A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond. In: IEDM Tech. Dig., pp. 31–34 (2007)

    Google Scholar 

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Joodaki, M. (2013). Logic Devices. In: Selected Advances in Nanoelectronic Devices. Lecture Notes in Electrical Engineering, vol 175. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31350-9_2

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