Abstract
Utilization of adaptive algorithm for fair bandwidth allocation, low latency and maximum CPU utilization is proved to be a promising approach for designing system-on-chip for future applications. Adaptive arbitration is more advantageous then the other conventional arbitration algorithms for several reasons; these include fair bandwidth allocation among different masters, simple design and low cost over head. This article provides a comprehensive picture of research and developments in dynamic arbitration algorithm for masters according to the different traffic behavior. The papers published in standard journals are reviewed, classified according to their objectives and presented with a general conclusion.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Pasricha, S., Dutt, N.: On–Chip Communication Architectures: System-on-Chip Interconnect. Morgan Kaufmann, USA (2008)
Poletti, F., Bertozzi, D., Benini, L., Bogliolo, A.: Performance Analysis of Arbitration Policies for SoC Communication Architectures. Des. Autom. Embed. Syst. 8(2), 189–210 (2003)
Jian, W., Yubai, L., Qicong, P., Taiqiu, T.: A Dynamic Priority Arbiter for Network-on-Chip. In: IEEE International Symposium on Industrial Embedded Systems, pp. 253–256. IEEE Press (2009)
Antonopoulos, C., Dimitrios, S.N., Theodore, S.P.: Scheduling Algorithms with Bus Bandwidth Considerations for SMP’s. In: IEEE International Conference on Parallel Processing, pp. 547–554. IEEE Press (2003)
Laxmi, N.B.: Analysis of Interconnection Networks with Different Arbiter Designs. J. Parallel Distrib. Comput. 4(4), 384–403 (1987)
Lakshmi, V., Wood, K., Downs, T.: A Four-Channel Communications Arbiter for Multiprocessor Arrays. Microprocess. Microsyst. 18(5), 253–260 (1994)
Macii, E., Poncino, M.: Automatic Synthesis of Easily Scalable Bus Arbiters with Dynamic Priority Assignment Strategies. Comput. Electr. Eng. 24(3), 223–228 (1998)
Nelson, J.C.C., Refai, M.K.: Design of a Hardware Arbiter for Multi Microprocessor Systems. Microprocess. Microsyst. 8(1), 21–24 (1984)
Bowen, B.A., Buhr, R.J.A.: The Logical Design of Multiprocessor Systems. Prentice Hall, Englewood Cliffs (1980)
Yi, X., Li, L., Ming-lun, G., Bing, Z., Zhao-yu, J., Gao-ming, D., Wei, Z.: An Adaptive Dynamic Arbiter for Multi-Processor SoC. In: 8th IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 1993–1996. IEEE Press (2006)
Aravind, A.A.: An Arbitration Algorithm for Multiport Memory Systems. ELEX 2(19), 488–494 (2005)
Chien-Hua, C., Geeng-Wei, L., Juinn-Dar, H., Jiang-Yang, J.: A Real Time Bandwidth Guaranteed Arbitration Algorithm for SoC Bus Communication. In: 11th Asia and South Pacific IEEE International Conference on Design Automation, pp. 24–27. IEEE Press (2006)
Haishan, L., Ming, Z., Wei, Z., Dongxiao, L.: An Adaptive Arbitration Algorithm for SoC Bus. In: IEEE International Conference on Networking, Architecture and Storages, pp. 245–246. IEEE Press (2007)
Bourgade, R., Rochange, C., De Michiel, M., Sainrat, P.: A Multi-Bandwidth Bus Arbiter for Hard Real Time. In: IEEE 5th International Conference on Embedded and Multimedia Computing, pp. 1–7. IEEE Press (2010)
Shanthi, D., Amutha, R.: Performance Analysis of On-Chip Communication Architecture in MPSoC. In: IEEE International Conference on Emerging Trends in Electrical and Computer Technology, pp. 811–815. IEEE Press (2011)
Shanthi, D., Amutha, R.: Design of Efficient On-Chip Communication Architecture in MPSoC. In: IEEE International Conference on Recent Trends in Information Technology, pp. 364–369. IEEE Press (2011)
Trahay, F., Brunet, E., Denis, A.: An Analysis of the Impact of Multi-Threading on Communication Performance. In: IEEE International Symposium on Parallel & Distributed Processing, pp. 1–7. IEEE Press (2009)
Scarabottolo, N., Bedina, A., Distante, F.: Implementation Guidelines of a Modular General Purpose Multi-Microcomputer. J. Syst. Architect. 9(5), 309–313 (1982)
Ruibing, L., Aiqun, C.: SAMBA Bus- A High Performance Bus Architectures for System-on-Chips. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 15(1), 69–79 (2007)
Lin, B.C., Lee, G.W., Huang, J.D., Jou, J.Y.: A Precise Bandwidth Controller Arbitration Algorithm for Hard Real-Time SoC Buses. In: Asia and South Pacific IEEE International Conference on Parallel & Design Automation, pp. 165–170. IEEE Press (2007)
Akhtar, M.N., Sidek, O.: An Arbiter with Fair Bandwidth Allocation and Low Latency for Real Time Computing System. In: International Conference on Computer Technology and Development, pp. 189–196 (2011)
Akhtar, M.N., Sidek, O.: An Intelligent Arbiter for Fair Bandwidth Allocation. In: IEEE Students Conference on Research and Development, pp. 322–327 (2011)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Akhtar, M.N., Sidek, O. (2012). An Adaptive Arbitration Algorithm for Fair Bandwidth Allocation, Low Latency and Maximum CPU Utilization. In: Benlamri, R. (eds) Networked Digital Technologies. NDT 2012. Communications in Computer and Information Science, vol 293. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-30507-8_29
Download citation
DOI: https://doi.org/10.1007/978-3-642-30507-8_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-30506-1
Online ISBN: 978-3-642-30507-8
eBook Packages: Computer ScienceComputer Science (R0)