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A New Scan Attack on RSA in Presence of Industrial Countermeasures

  • Jean Da Rolt
  • Amitabh Das
  • Giorgio Di Natale
  • Marie-Lise Flottes
  • Bruno Rouzeyre
  • Ingrid Verbauwhede
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7275)

Abstract

This paper proposes a new scan-based side-channel attack on RSA public-key cryptographic implementations in the presence of advanced Design for Testability (DfT) techniques. The attack is performed on an actual hardware implementation, for which different test scenarios were conceived (response compaction, X-Masking). The practical aspects of scan-based attacks on the RSA cryptosystem are also presented. Additionally, a novel scan-attack security analysis tool is proposed which helps in evaluating the scan-chain leakage resilience of security circuits.

Keywords

Scan-attacks public-key cryptography DfT methods 

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References

  1. 1.
    Yang, B., Wu, K., Karri, R.: Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. In: Proceedings IEEE International Test Conference, ITC (2004)Google Scholar
  2. 2.
    Yang, B., Wu, K., Karri, R.: Secure Scan: A Design-for-Test Architecture for Crypto Chips. In: Proceedings ACM/IEEE Design Automation Conference (DAC), pp. 135–140 (June 2005)Google Scholar
  3. 3.
    Sengar, G., Mukhopadhayay, D., Chowdhury, D.: An Efficient Approach to Develop Secure Scan Tree for Crypto-Hardware. In: 15th International Conference on Advanced Computing and CommunicationsGoogle Scholar
  4. 4.
    Inoue, M., Yoneda, T., Hasegawa, M., Fujiwara, H.: Partial Scan Approach for Secret Information Protection. In: European Test Symposium, pp. 143–148 (2009)Google Scholar
  5. 5.
    Nara, R., Satoh, K., Yanagisawa, M., Ohtsuki, T., Togawa, N.: Scan-Based Side-Channel Attack Against RSA Cryptosystems Using Scan Signatures. IEICE Transaction Fundamentals E93-A(12) (December 2010), Special Section on VLSI Design and CAD AlgorithmsGoogle Scholar
  6. 6.
    Wang, L.-T., Wen, X., Furukawa, H., Hsu, F.-S., Lin, S.-H., Tsai, S.-W., Abdel-Hafez, K.S., Wu, S.: VirtualScan: a new compressed scan technology for test cost reduction. In: Proceedings of International Test Conference, ITC 2004, October 26-28, pp. 916–925 (2004)Google Scholar
  7. 7.
    Rajski, J., Tyszer, J., Kassab, M., Mukherjee, N.: Embedded deterministic test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(5), 776–792 (2004)CrossRefGoogle Scholar
  8. 8.
    Mitra, S., Kim, K.S.: X-compact: an efficient response compaction technique for test cost reduction. In: Proc. ITC 2002, pp. 311–320 (2002)Google Scholar
  9. 9.
    Liu, C., Huang, Y.: Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance. In: 25th IEEE VLSI Test Symposium, VTS (2007)Google Scholar
  10. 10.
    Nara, R., Togawa, N., Yanagisawa, M., Ohtsuki, T.: Scan-Based Attack against Elliptic Curve Cryptosystems. In: Asia South-Pacific Design Automatic Conference, ASPDAC (2010)Google Scholar
  11. 11.
    Liu, Y., Wu, K., Karri, R.: Scan-based Attacks on Linear Feedback Shift Register Based Stream Ciphers. ACM Transactions on Design Automation of Electronic Systems, TODAES (2011)Google Scholar
  12. 12.
    Das, A., Knezevic, M., Seys, S., Verbauwhede, I.: Challenge-response based secure test wrapper for testing cryptographic circuits. In: IEEE European Test Symposium, ETS (2011)Google Scholar
  13. 13.
    Hély, D., Flottes, M., Bancel, F., Rouzeyre, B., Berard, N., Renovell, M.: Scan Design and Secure Chip. In: 10th IEEE International On-Line Testing Symposium, IOLTS 2004 (2004)Google Scholar
  14. 14.
    Hély, D., Bancel, F., Flottes, M., Rouzeyre, B.: Test Control for Secure Scan Designs. In: European Test Symposium, ETS 2005 (2005)Google Scholar
  15. 15.
    Da Rolt, J., Di Natale, G., Flottes, M., Rouzeyre, B.: New security threats against chips containing scan chain structures. Hardware Oriented Security and Trust, HOST (2011)Google Scholar
  16. 16.
    Da Rolt, J., Di Natale, G., Flottes, M., Rouzeyre, B.: Scan attacks and countermeasures in presence of scan response compactors. In:16th IEEE European Test Symposium, ETS (2011)Google Scholar
  17. 17.
    Menezes, A., van Oorschot, P., Vanstone, S.: Efficient Implementations. In: Handbook of Applied Cryptography, ch. 14. CRC Press (1996)Google Scholar
  18. 18.
    Gezel Hardware/Software Codesign Environment, http://rijndael.ece.vt.edu/gezel2/

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Jean Da Rolt
    • 1
  • Amitabh Das
    • 2
  • Giorgio Di Natale
    • 1
  • Marie-Lise Flottes
    • 1
  • Bruno Rouzeyre
    • 1
  • Ingrid Verbauwhede
    • 2
  1. 1.LIRMMUniversité Montpellier II /CNRS UMR 5506MontpellierFrance
  2. 2.ESAT/COSICKatholieke Universiteit LeuvenLeuvenBelgium

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