Abstract
In this paper a method for processors arrays design dedicated to realization of specimen linear algebra algorithms in FPGA devices is presented. Within an allocation mapping process a genetic algorithm for information dependency graph projection is used and the runtime of the given algorithm is optimized. For larger input matrices, graph decomposition is used which allows the projection results to be obtained. The obtained projection results, with and without graph decomposition, for a specimen linear algebra algorithm are compared. Additionally, a parallel realization of the evolutionary algorithm for multicore processors is presented, which allows projection results to be obtained for larger input matrix sizes.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Peterson, M.: FPGA Acceleration for outstanding performance. Challenges and Opportunities. In: Parallel Processing and Applied Mathematics, Wroclaw, Poland (2009)
Kestur, S., Davis, J., Williams, O.: BLAS Comparision on FPGA, CPU and GPU. In: IEEE Computer Society Symposium on VLSI (2010)
Williams, J., George, A.D., Richardson, J., Gosrani, K., Suresh, S.: Computational Density of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration. In: Proc. 4th Reconf. Sys. Inst., Nat’l Center for Supercomp. App., Illinois (2008)
Chen, Y.K., Kung, S.Y.: Trend and Challenge on System-on-a-Chip Designs. Journal of Signal Processing Systems 53, 217–229 (2008)
Maslennikow, O.: Podstawy teorii zautomatyzowanego projektowania reprogramowalnych równoległych jednostek przetwarzajacych dla jednoukładowych systemów czasu rzeczywistego. Wyd. Uczelniane Politechniki Koszalińskiej, stron 273 (2004)
Ratuszniak, P., Maslennikow, O.: New Conception and Algorithm of Allocation Mapping for Processor Arrays Implemented into Multi-Context FPGA Devices. Mathematica Balkanica 23 (2009)
Kung, S.Y.: VLSI Array Processors. Prentice Hall, Englewood Cliffs (1988)
Quinton, P., Robert, Y.: Systolic algorithms and architectures. Prentice Hall (1991)
Sergyienko, A., Kaniewski, J., Maslennikow, O., Wyrzykowski, R.: A metod for mapping DSP algorithm into application specific processor. In: Proc. 24th Euromicro Conference on Parallel and Distributed Processing, vol. 1. IEEE Comp. Soc. Press, Vasteras (1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Ratuszniak, P. (2012). Processor Array Design with the Use of Genetic Algorithm. In: Lirkov, I., Margenov, S., Waśniewski, J. (eds) Large-Scale Scientific Computing. LSSC 2011. Lecture Notes in Computer Science, vol 7116. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29843-1_27
Download citation
DOI: https://doi.org/10.1007/978-3-642-29843-1_27
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-29842-4
Online ISBN: 978-3-642-29843-1
eBook Packages: Computer ScienceComputer Science (R0)